Re: request for help

["Myron Plichota" <myron.plichota@xxxxxxxxxxxx>]

Dear Yasser,

Different vendors implement the inner workings of their VHDL toolchains
differently, and the intermediate files visible to the designer seem to be
optimized for whatever silicon technology (eg. CPLD, FPGA, gate-array,
full-custom) the vendor is in the business of selling. So far I have used
Xilinx Foundation, Cypress Warp 2, and Atmel Everest VHDL tools and none of
the details you are concerned with have mattered, however the post-fitting
report files can be extremely revealing. I have tested the portability of
VHDL designs between different vendors' tools and have only found it
necessary to make minor changes to the source files (mostly with respect to
library specifications) in order for successful compilations to take place.
 Like GNU C, VHDL source is nearly but not quite 100% portable. I suggest
that you simply experiment with editing, compiling, and simulating designs
with whatever toolchain you can get your hands on so that you can gain
confidence in specifying the design in VHDL, rather than fixating on how
things may or may not work "under the hood".

Myron Plichota

----------
From: yaserh <yaserh@gega.net>
To: misc@pisa.rockefeller.edu
Subject: request for help
Date: Monday, August 28, 2000 1:46 PM

Dear Jeff Fox :

I read your reply for  "P16 VHDL". I'm beginner to vlsi design and i'm now
trying to learn VHDL and i need from you some guide on the steps i can
follow to be able to design chip. 
 
* I need also to know is the Vhdl compiler generate the RTL output or there
is any other tool which generate the RTL output. 
 
* Also i need to know after generating the RTL output how i can generate
the complete structural design and what is the tool that generate the
structural design. 

* I need also to know is the structural design will be in the form of gates
or transistors and how this structural design be transfered to the
technology i will fabricate the chip.

With my best regards
Yasser El-haddad