[ColorForth] 25x graphics

[Mark Slicker <maslicke@xxxxxxxxxxx>]

On Thu, 13 Dec 2001, Mark Sandford wrote:

> The problem as it always seems to be is bandwidth.
> 
> 1024*768*72Hz = 56.6 MWords (assuming 18bit video)
> if this amount has to be read into and then pushed out
> this requires a net bandwidth of 112 MWords/Sec and the 
> SRAM spec'ed is only clocked at 200MHz with a two cycle
> latency so don't expect to get all the bandwidth anyway.
> A special video out port would help but, with 25 processors
> bandwidth was always going to be limited, especially with 
> the small per processor local memories.  If you only
> want NTSC/PAL video then there isn't much of a problem
> but you really need dedicated video resources for the
> higher resolutions/bandwidths.
> 

You point to a valid problem. The approach I was thinking of doesn't
require a frame buffer. However, I do expect things like images and maybe
a character cache to be put in SRAM. Perhaps the character cache could
even be put on chip. An image the size of screen would be equivalent to
the frame buffer problem, of course a image this size wouldn't fit in the
SRAM in the first place. Perhaps compression could be used? The renderer I
was thinking of would be a trapazoidal renderer. This would perform
trapaziodalization in the vertical blanking period, and compute spans at
each horizontal blanking period, perhaps during the output too. I need to
work these ideas out some more, there might be better ways to do
rendering. When the chip simlutaor is made available I'll probably have a
better idea what is possible. It does seem like a workable idea. There
might be tradeoffs required in resolution for more mips/fewer memory
accesses.

Mark


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