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RE: [colorforth] Realtek Ethernet driver

Hi Mark & Oninoshiko,

Yes this list is much too quiet...

< sound of applause >

Well done for attacking the beast that is TCP !
And its guardians, those who hide meaningful documentation about NICs!

Keep up the good work ;)

Howerd

-----Original Message-----
From: Mark Slicker [mailto:maslicke@xxxxxxxxxxx]
Sent: 07 June 2004 20:09
To: ColorForth Mailing List
Subject: Re: [colorforth] Realtek Ethernet driver


On Sun, 6 Jun 2004, Oninoshiko wrote:

> On Sun, 6 Jun 2004, Mark Slicker wrote:
>
> > The FIFO buffer is an intermediate step. Once a threshold is met the
> > packet is transfered by the realtek card from the FIFO to host (main)
> > memory. This operation is enabled by setting a bit in the Command
> > Register on the realtek chip, and is independent of whether interupts
are
> > enabled either on the CPU or the realtek chip.
>
> I stand corrected, on rereading, the buffer (main/host memory?) is a
> cyclic buffer (8k+1536b overrun?). It looks like I have registers to
> tell me where in this buffer I am (37h bit 0 (RX Buffer Empty), 38h-39h
> (CAPR)). i wanted to conferm this.

It says it is a ring buffer, I think that implies a cyclic buffer. I don't
see anywhere in the rtl8139b documentation a precise description of the
operation. Chuck uses (CAPR + 16 + rx + 4) as the address of the
recieved packet, I not quite sure how this is derived. In addition he sets
CAPR to (CBR - 16) and CBR to 0.

> > The interrupt is used for signaling. Chuck has enabled the ROK (Recieve
> > OK) interupt, which will signal when a packet has succesfully been
> > recieved to host memory.
>
> am i understanding this correctly?

As well as I do it seems, the documentation is not a clear as it could be.

>
> thanks for all your help,
>

No problem, and besides this list is much to quiet! ;)

Mark

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