Re: [colorforth] Musings on SEAForth
- Subject: Re: [colorforth] Musings on SEAForth
- From: Luis <forth@xxxxxxxxxxxxxxx>
- Date: Tue, 22 Jan 2008 00:27:59 +0000
- Organization: aNaCHReoN
This somewhat reminds me of Objective Programming, except, it's in
hardware, or rather _is_ the hardware: Objective Hardware? Like each
node is a cell, with a specific purpose/task/function.
Cheers,
Luis.
John R. Strohm wrote:
You do what someone else did.
You design a meta-architecture, that looks like you want it, such that
each meta-instruction can be interpreted by a sequence of not more than,
say, 32 core instructions. You stash those routines in a known place in
memory.
You then dedicate one core as a memory controller, that fetches words
from external memory on command. You dedicate a second core as a
meta-fetcher, that requests a word from the first core, decodes it just
far enough to see which meta-instruction interpret routine is needed.
The meta-fetcher then commands the memory controller to pull in the
routine, which may be executed by the meta-fetcher, or may be sprayed at
a third core.
You then write an integer BASIC interpreter, in your meta-architecture,
and stash that in memory somewhere else.
At some point in this process, you realize that you have reinvented
vertical microprogramming, the Sweet16 interpreter, and Integer Basic,
from the earliest days of the Apple II.
One is drawn to speculate that high data bandwidth, how much data you
can move THROUGH the chip, was not a design goal, but high INSTRUCTION
bandwidth, how many instructions you can execute per data point, was.
This makes the chip suitable for certain very compute-intensive
applications, such as ray-tracing, and not so suitable for I/O-bound
applications, such as a specialized image processing problem I worked
some years ago.
----- Original Message ----- From: "M. Edward (Ed) Borasky"
<znmeb@xxxxxxxxxxx>
To: <colorforth@xxxxxxxxxxxxxxxxxx>
Sent: Monday, January 21, 2008 9:41 AM
Subject: [colorforth] Musings on SEAForth
2. How one would fit a large complex program to an array of these
devices. While Forth is certainly a multi-level language eminently
suitable for designing domain-specific languages, I don't see how you
could *automatically* go from a high-level problem description to
working hardware and software, especially with the cores having a ROM
component!
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