No Subject

[jfox@xxxxxxxxxx (Jeff Fox)]

Frank asked several questions about F21 and P8.

F21 will have several new coprocessors and several changes to the cpu in
addition to being done in .8 micron technology.

F21 info is still preliminary as the design is not finished.  Chuck has
given me specs, but they do not include the details of the video and
network processors.  Most of the info on the cpu, analog coprocessor,
and 8 bit parallel i/o port is available.  I have not posted this info
as I have been waiting for the final specs on the serial/network interface
and video a/d-d/a coprocessors.  But I will post the partial info that I
do have in this mail list.

CPU:
The F21 CPU will have deeper stacks than MuP21.  It had 16 levels on the
data and return stacks last time I saw it.  I asked for 32 levels, and we
may get close to that.  Perhaps 32 on the return stack and 28 on the data
stack.  They will take up as much room as they can and be as big as this
die will permit.  There are two instructions added, @R+ and !R+.  These
access memory via the top of the return stack.  Jump and call instructions
will be expanded to accept a 15 bit argument if they appear in the first
slot, so on page 10 bit address AND 15 bit offpage addresses will be
available in  single word instructions.  There will also be a gray code
register to read the stack depths.  Instructions should execute in 4 or
5ns. Also 3 more pins are used to expand the size of the high speed
20 bit wide SRAM space from 1k to 8k.  The setup time for memory will
be much faster than MuP21 because of .8 micron and more power and
ground pins.  The goal is to get a 5ns setup time so 15ns SRAM can
be accessed every 20ns.  (5ns instructions and memory access every 20ns
is 200 mips)  OVER will be replaced with SWAP.

Video:
Input and output will be supported.  Software should provide genlock and
video overlay, digitization, and decoding of digital information in a
standard video signal format.  4 bit resolution like MuP21, but with
a potentially higher clock rate.  3 more pins have been provided for
RGB output in addition to composit.

Analog:
The analog i/o coprocessor will be fast enough for 6 bit video (14 mhz)
but will normally be used for audio.  Higher resolution than 6 bits will
be available with oversampling and pwm techniques.

Parallel i/o:
An 8 bit bi-directional i/o port will be provided on chip.

Serial/Network:
The serial/network coprocessor is designed to provide hardware support
for multiprocessing, networking, or serial i/o.  It sends and receives
packets of data with addressing bits.  It will support DMA and 
network initiated CPU interrupts.  This provides a hardware mechanism
for distributed/sharred memory and remote program execution.  The
unit is designed for a maximum of 1 gigabit/sec throughput.   We will
determine the maximum speed of data flow and and off chip experimentally.
Chuck's estimate at this time is 400 or 500 mbps.

The .8 micron process has required different design rules, and every
transistor on MuP21 has had to change to make F21.  But it has many
architectural features sharred with MuP21.  F21 will no longer use
instruction bit interleaving, but will still use the complementary
polarity bus structure used in MuP21. (ie. odd and even bits use a
different voltage to represent a 1) 

I will post the details given to me so far by Chuck.  They do not
include the details of the video or network processors.

Jeff Fox
11/16/94