No Subject

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear Mark and other MISC readers,

>We havn't heard much abount the progress on the F21. 
>How is development going??
>I'm particularly interested in the characteristics of the serial port,
>	- what data format
>	- what speed
>	- interface to rest of chip
>	- compatable with what ????
>	- ......
>Hope all is going well in development, when might first silicon be
>expected ???
>
>Thanx in advance.
>Best wishes for a great 95.
>
>Mark Sandford

Yes, F21 has slipped to let a P8 prototype go down the line at
MOSIS.  MuP21 was done at ORBIT and every transistor has changed from
MuP21 to F21.  MOSIS uses a different set of rules, so Chuck will 
have to get working chips from this process to verify the simulations
on the CAD  system.
P32 will be using the cpu core from F21 in an expanded form, and
F21 will be prototyping some stuff going into P32.
The latest word from Chuck was that P8 prototypes will be back soon.
Chuck was talking about submitting F21 for prototypes in Feb, but
it could always slip.
F21 design is not complete.  The serial/network interface  is still
under construction.  Chuck has not completed this unit, so the
details are not available.
Data Format ?
Speed ?  I  expect 9600 to 100mbps perhaps more.  The upper limit
on the memory bus is 1 gigahertz and the device will run at up
to that speed on chip.  F21 may be able to run at several hundred
mbps, we will see.  P32 will be designed to actually get gigahertz
signals on and off chip.  It appears that there will be one external
clock input and the i/o devices will all use the same external clock
frequency.     
Interface to the rest of the chip ? - mostly unknown.  It will
support dma and cpu interupts on individual addresses and groups.
There will be  some registers to set, and address restrictions
perhaps even data restrictions, but details are not known.  It
is a coprocessor, reading instructions from the serial stream.
Compatible with what? - other F21.  It may be able to do standard
8 bit serial data formats, we will see.

I have most of the details on the rest of the chip, but this
stuff is all still preliminary.  I have been waiting to get the
specs on the serial/network interface to release a complete
description.

I am not sure how much information on P8 and P32 is public. But
I can say that a P8 has slipped in front of F21 in the 
prototype line.  As we are still trying to keep expenses down it
makes sense to test certain things on the cheaper P8.  There is
a certain delay needed to get apply what is learned from
chips returned by the process.

Feel free to ask.  I will post updates as I get the information.
I am particularly interested in the details of Chuck's
implementation of the serial/network coprocessor.  I cannot write
any actual code until I get some details from Chuck.

I will let people know when I do.
Jeff Fox