Sequencing of instructions -- latching of results
On Tue, 18 Apr 1995, Dave Lowry wrote:
> > Consider this instruction sequence:
> > a! @+ a dup
> > dup -or com nop
> > +
> >
> > This is a distillation of the steps used to increment then decrement
> > the stack pointer. Let's say that TOS is set to pattern 000001, and
>
>
> Could someone explain to me how instructions are sequenced? Why is
> the nop *before* the +? I would expect the sequence to go:
> + nop nop nop <instruction fetch>
> or:
> --- --- --- + <instruction fetch>
>
> So that nops are required *after* the +, or an instruction fetch to allow
> for carry prop. Thanks.
This most definitely should be in the FAQ.
Jeff had managed to explain it clearly enough (to me at least :-) once, but I
couldn't find it easily in the archive, so here is my view on the subject.
The instructions are not sequenced. All (arithmetic) instructions have their
own ALUs, so everything executes in parallel. When the time of the
instruction comes, the opcode is used as an index to a table of already
computed results, one of which is coppied to TOS. Some of the bits of the
opcode can be used to trigger stack manipulations, but this is another story.
For example, the ALU for and starts a new cycle each time the stack is
changed. By the end of the cycle, the result is computed. If the current
instruction happens to be and, the result is coppied to TOS and SOS i
dropped.
The + ALU seems to have an internal state, which remembers the current
carries. It is cleared each time the stack is changed and a new cycle
starts. If the stack doesn't change, as in nop, the carries are left intact
to propagate. In all cases, when + comes in the stream, the current register
is coppied to TOS and the SOS is dropped.
+n seems to latch the + ALU contents conditionally on TOS0, and not drop SOS.
I guess Jeff will add clarifications, if this is not the (whole) story.
--
Penio Penev <Penev@venezia.Rockefeller.edu> 1-212-327-7423
