No Subject

[jfox@xxxxxxxxxx (Jeff Fox)]

From: Penio Penev <penev@pisa.rockefeller.edu>

>I remember hearing Chuck saying some months ago that with the technology
>of MuP21 he can make memory (stacks) abot 1000 times more expensively than
>the with the technology semiconductor companies make DRAM with. (Whatever
>that means.)

There are several reasons for Chuck saying this, first he does not
know how to design efficient random access memory.  He can put memory
on chip the form of stacks, or registers, cache, or rom, or sram, or
even dram.  But it is not going to be very dense or very effient compared
to memory chips.  He points out that even the cache memory on the
state of the art microprossors is orders of magnitude more expensive
than off chip memory.  You pay a couple of thousand dollars for the
on chip cache memory on the hottest microprocessors, and get only 100k
at most.  Compare that to high denstiy memory costs.  
Also Chuck cannot make cache, rom, registers or other on chip memory
that is as dense as the arrays laid out in mormal chips with cache etc.
The advantages to his design are not high density (expensive) on chip
memory, but very small alu and  tight integration of all the parts.

Memory chips not only use things like .35 micron but also many more 
layers in the fab process than the technology that Chuck has access to.

So if Chuck studied how to design memory, and had access to the
state of the art fab processes he could integrate his designs very
tightly with lots of on chip memory.   This is not going to happen in
the near future from the way I see it.                  

Chuck doesn't presently know how to design efficient memory, and as
he points out, on chip memories are usually many many times less efficient
than the state of the art memory chips themselves.

So unless Chuck gets a big change in direction I don't think he is
going to catch up, or pass the memory makers.  He may be able to catch
up to and pass the cpu designers if he gets access .6, .5, .35, etc.

>If one factors the better geometry of the new stack designs, and the 0.8u
>technology of the F21. This ratio could have been improved a bit, but most
>definitely not 1000 times :-(

Sure.  P21 has only 11 registers, 231 bits of memory in stacks, and A.
(not counting PC and the config register)  F21 has about three times
that many on chip bits,  but that is orders of magnitude less than
memory chips with megabits of memory!

>There are always the questions can processors be made with the advanced
>memory technology, and can a hybrid be made cheaply enogh. I have
>absolutely no clue about it. 
>
>--
>Penio Penev <Penev@venezia.Rockefeller.edu> 1-212-327-7423

I still like the idea of a fast processor in the corner of a big fast
memory chip.  The processor is the trivial part of the problem.  The
problem is the state of the art memory chips, that is why those
memory chips are not being made here.  It is a very fast moving
technology, and even more expensive than the processor design business.

I would really like a P32 or P64 with a bunch of megabytes on chip,
and a bunch of gigabit  communication lines, you wouldn't need to
run the address and data busses off chip, so you could put it in
a tiny little chip package.  Just power and i/o pins.  

Jeff Fox