Re: a modified DRAM die with a MISC?

[MSANDFORD@xxxxxxxxxx]

>On Thu, 11 May 1995, Eugen Leitl wrote:
>
>> is there a basical (that means technical, not financial)
>> difficulty to integrate a MISC core, particularly a ultra-wide
>> data bus one as a integral part of (slightly modified)
>> standard DRAM die (e.g. a 1-4MBit one)?
>
>I remember hearing Chuck saying some months ago that with the technology
>of MuP21 he can make memory (stacks) abot 1000 times more expensively than
>the with the technology semiconductor companies make DRAM with. (Whatever
>that means.)

I can certainily understand that it would be nearily impossible to implement
a large amount of RAM (SRAM or DRAM) on chip.   Even the RAM suppliers
are having troble making it fast and large and as such only a few can compete
in the memory market in which there is consummer demand that always
outstrips supply no matter how many new factories come on line.  So being
that it is not feasible to do it all on the same chip can we still get the
benifits
by side stepping the problem and using integration?????.   As some of you
may or may not be aware the P6 ( 80686 a.k.a.  sucessor to the Pentium) is not
a chip in the normal sense but a multi-chip module with two large dies.  The
first
is a large CPU with (I think) 16K cache that operates as the fist level cache
ussually
called L1 and the second chip is 256K of secondary cache (L2).  If desired the
board
manufacturer can implemet an L3 and L4.  This is becomming fairily standard in
high
performance RISC systems (to have multiple levels of cache) with each
sucessive
level being deeper than the first and