Re: a modified DRAM die with a MISC?

[MSANDFORD@xxxxxxxxxx]

I accidentally sent the previous message off before I was
finished so the first half is a repeat.  If you read the last message
jump to the middle and finish up otherwise ignore my
rantings and hit delete.






>On Thu, 11 May 1995, Eugen Leitl wrote:
>
>> is there a basical (that means technical, not financial)
>> difficulty to integrate a MISC core, particularly a ultra-wide
>> data bus one as a integral part of (slightly modified)
>> standard DRAM die (e.g. a 1-4MBit one)?
>
>I remember hearing Chuck saying some months ago that with the technology
>of MuP21 he can make memory (stacks) abot 1000 times more expensively than
>the with the technology semiconductor companies make DRAM with. (Whatever
>that means.)

I can certainily understand that it would be nearily impossible to implement
a large amount of RAM (SRAM or DRAM) on chip.   Even the RAM suppliers
are having troble making it fast and large and as such only a few can compete
in the memory market in which there is consummer demand that always
outstrips supply no matter how many new factories come on line.  So being
that it is not feasible to do it all on the same chip can we still get the
benifits by side stepping the problem and using integration?????.   As some of
you
may or may not be aware the P6 ( 80686 a.k.a.  sucessor to the Pentium) is not
a chip in the normal sense but a multi-chip module with two large dies.  The
first is a large CPU with (I think) 16K cache that operates as the fist level
cache
ussually called L1 and the second chip is 256K of secondary cache (L2).  If
desired the
board manufacturer can implemet an L3 and L4.  This is becomming fairily
standard in
high performance RISC systems (to have multiple levels of cache) with each
sucessive level being deeper than the previous and slowwer, to save on cost.

While this isn't exactily what a MISC processor wants.  Would it be possible
to build a multi-chip module with some amount of fast SRAM ???? This would
have a number of benifts namely speed and reduced pin count.  As an example
it might be possible to put five   64K x 4 -15 ns  SRAMS together with a F21.
This would give 160K of memory and with its network connections you could
live without all the external data and address lines.  So this allows you to
have
a small in size  parallel processing machine with huge amounts of MIPS.  Chuck
has claimed that the external interface is the only thing limiting the speed
of the
processor so lets just drop it.   I beleive that Chuck has claimed that he
could run at
near Giga-hertz rates so why not exploit this by packaging high speed
comercial SRAM
dies with a really fast processor.    There should be tremendous performance
gains
by not having the data lines outside the chip and as such the 15 ns. SRAMs
could probably be run  much faster by restricting thier use to the fixed and
enclosed
environemnt of a multi-chip module.  I'm quite sure that this would be
sucessful
the question is how hard is it to get custom multi-chip modules made.

I have been working with the INMOS Transputer of the last five years, which
is a really interesting beast.  It's ability to talk to other processors over
a two
wire link is a tremendous capability not found in many other processors.  The
F21
is prommissing a similiar capability although with only two communication
ports
(I really consider four as minimium as two limits you to a line or ring
topology).
This ability with blazing speed would surely be big selling point.  Jeff Fox
has tried to extoll the very valid virtues of the MISC architecture, but I
think that
his arguments always seemed (atleast to me) fall a little flat as there are
many
other processors that either are faster or cheaper and as such the MISC
architecture doesn't break any technology edges.  In the book
_Accidental_Empires_
by Robert X Cringley (one of my favorite books) he puts forth that a theory
that for
of a product to be sucessful it has to break two market edges.  If a MISC
processor
could be marcketed with a clock speed faster that the current 300 MHz Alphas
it
would get immediate market attention.  I beleive that the future of computers
(atleast
high performance ones) lies in parallel processing,  I don't beleive that
shared
memeory architectures  will last too much longer as memory bandwidth is
limited
and each processor added ups demand with a constant supply.  To that
end distributed memory architectures with fast inter-node communications
will be required.  So if a F21 could be built using its fast communictions and
that paired with fast memory using a multi-chip module concept from above,
you could make a major technology break-through.

Well I guess that its time to finish "RANTING",  and get some work done but I
think that there is atleast the starting of some valuable ideas above, any
comments???

Mark Sandford
msandford@delphi.com