No Subject

[jfox@xxxxxxxxxx (Jeff Fox)]

Subject: MuP21 Memory Map / Memory Mapped I/O

Dear MISC readers,

Last Saturday Chuck gave a talk to the Silicon Valley FIG about P8,
F21, and P32.  I will be posting a review of it here and in c.l.f.

One thing that I noticed was he discussed SRAM addressing on MuP21
and I realized something that I had not understood properly.

This is because I have not actually worked with system with high
speed 20 bit wide SRAM, and the documention had not been clear.

Chuck said there were two signals on chip that he had been calling I/O
and SRAM.  He said that he was now using the more accurate names RAM
and ROM.  (I actually like the 8RAM just as well for ROM.)  The
point being that I/O IS memory mapped on MuP21 and on the boards
being used I/O is being mapped in 20 bit wide SRAM space!

This means two things:  the documentation of the memory map needs to
be changed, and the design of any high speed 20 bit wide
SRAM interfaces needs to be changed.

patterns ( the physical pattern on the address bus)

000000-0FFFFF 20 bit wide DRAM  1K pages 100ns extra time for off page access  
100000-13FFFF  8 bit (ROM/SRAM/PCMCIA) SLOW 250 ns (4 pages to outside world)
140000-17FFFF  8 bit (ROM/SRAM) FAST 40ns (4 pages to outside world)
180000-1803FF 20 bit (ROM/SRAM) SLOW 250ns
1C0000-1C03FF 20 bit (ROM/SRAM) FAST 40ns 
1E0000        20 bit configuration register      

(XOR these patters with AAAAA for numeric representation on MuP21.)

The system must map I/O somewhere into this memory on MuP21, and the
boards currently do it in the 1K slow or high speed 20 bit wide SRAM spaces.
So if anyone is going to set up a system to actually use high speed
20 bit SRAM this means they will have to change the place that I/O is
decoded from the one used on the kit.  You may think of the MuP21 as
physically address 1 megaword of DRAM, 1 megabyte of fast or slow 8 
bit wide sram, and 1K words of fast or slow 20 bit wide SRAM.  I
did not remember that the 1K i/o addresses ( in the current systems)
are the same as the 1K 20 bit wide SRAM interface addresses.

So for anyone designing parts using the 20 bit wide 1K space on P21
will need to move the I/O address space somewhere else.

You will need a FAST external circuit to decide on splitting the 40ns
space between I/O and SRAM, a much slower circuit could split one
of the SLOW address spaces, and since you boot from slow memory
that seems the logical place to me.

It seems to me the easiest way to do this would be use the bit A19
which is actually set with one of the bits in the configuration 
register.  This way one of the pages would give 256k 8 bit sram
locations and another page would give you 256k I/O address locations.
You could do whatever you want with the other 8 bit SRAM address
bit from the configuration register, such as have 3 banks of 256kx8
SRAM.

There are limits to how much bus logic the MuP21 can drive.  This 
might be a factor, but I would think that using the above approach
could give 1K of 40ns SRAM, 768K of 8 bit SLOW BOOT SRAM (UVPROM etc)
and 256k 8 bit I/O ports.           

So for the P21 FAQ or whatever, I think the above address map is
correct, and I think the explanation of the use of memory mapped I/O
on MuP21 is also correct.

Jeff Fox