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[jfox@xxxxxxxxxx (Jeff Fox)]

Subject: Scott McLoughlin, would you comment?
 
Dear MISC readers,

As Penio pointed out we considered making A stack with a few cells.
The ring idea would also be very useful.  We chose to use R as a
second memory addressing register for several reasons.   Mostly having
to do with instruction decode.  Two memory addressing registers that
are both available at the same time is also useful.
 
>ferinstance...
>Let's say the MISC address register grows into a special 16 cell stack, 
>where each cell has 8 additional bits which constitute two 4 bit pointers 
>to other cells in the same address stack. The main pointer ( actually, 
>pointer stack may be a better name for this entity) points to the object 
>in memory, the object or atom. 
> 
>Question: what Lisp-like things can be done with this critter, in how 
>many instructions additional to those required by a plain address 
>register/stack? 
> 
>Rick Hohensee

I am sure you could do some nice things with this design.  However there
would be some overhead to this address stack.  If it is not 21 bits wide
like the other internal registers then it would talk multiple instructions
to set up a value in this proposed 29 bit wide stack.
Also what you describe is combination of a stack machine and a general
purpose register machine with a special stack index indirect addressing
mode.  An interesting idea, but my guess is that it would be several times
larger than the entire MuP21 chip, and it might slow everythings else down
by at least a factor of two.  MuP21 can only run at the speed of the slowest
thing.   A 16 deep 29 bit wide stack would be several times larger than P21.
Then if it is also to be used a registers that can be indivitually addressed
add thousands of more transistors to accomplish this.  Then if the instructions
to use this must perform a register lookup and then an indirect reference to
memory it might slow the entire chip down by a factor of two.

So a second question is, would this feature be worth quadrupling the
development and production costs of the chip and reducing the execution
speed be a large factor?  It might be ten times more expensive and half the
speed, it is hard to say.  But it would be a major design change.

There are almost an infinite number of possible architectures.  An address
stack would be useful.  An indexable stack would be useful.  An indexed
indirect reference mechanism might be useful also.  The question is 
whether is seems useful enough to someone to actually pay to have it 
designed.

I did lots of simulations of changes to the P21 architecture to make the
F21 specs.  I wrote about 40 compilers and tested many aspects of the
system performance based on various changes to the instruction set and
architecture.  These results were balanced against how much each of
proposed changes would cost to develop, implement, and manufacture. It
was a very educational experience.  I recommend to anyone who is interested
in exploring new architectures to do the same.  Write a simulation of
a proposed architecture or instruction and write some code to use it,
then run tests and compare results.  If you find something is very
valuable then perhaps you can convince someone to actually do it.  If
you can't get a custom chip yourself you may influence the design of
some chip to do what you really would like it to do.

Jeff Fox