Re: 400 MIPS internally and carry propagation
On Mon, 29 May 1995, Jeff Fox wrote:
> Silicon Valley Chapter of the Forth Interest Group
>
> Meeting May 27 1995 10 am to 5 pm
> He said that the simulator currently says 400
> mips internally on F21, he said at one point he had it tuned to 500,
> but he worried he had pushed it too far. He said that generally there
> were no advantages to making it slower. If he slows things down the
> signals may not be as good. He said there was a sort of natural
> resonance for the design. His design has a ~300 picosecond delay for
> each of the various sort of primitive operations that occur on the
> the chip. It takes ten or twelve of these steps to execute a CPU
> instruction.
What are the implications of the fast internal speed on the NOPs,
needed for carry propagation?
One possible scenario is that all four instructions will be latched as
soon as the could, and then wait for a long time till the next four come.
Another scenario is that although the results are stable very quickly,
the latching is delayed, so that the overall waiting for the next
instruction to come is distributed among the four slots. This means, that
the carry for each individual slot will have more time to propagate, and
longer operands will be able to be added without a NOP.
The motivation is for the following code to work for as longer
operands, as possible:
+n 2/ +n 2/
This is a part of a multiplication, which in case of insufficient
carry propagation time would be carried out like this:
+n 2/ nop nop
thus slowing it twice. Of course, the best scenario is that the delay is
distributed only between the first and the third slots, so they are
stretched longer and accommodate longer add operands. This will make some
programs relying on multi-precision multiplication run twice as fast.
--
Penio Penev <Penev@venezia.Rockefeller.edu> 1-212-327-7423
