Re: parallel RETs
On Fri, 2 Jun 1995, Jeff Fox wrote:
> Penio asks:
> >Well, (inst inst RET +) may be useful from time to time if RET allowed
> >the instructions till the end to be executed. Is this the case with F21,
> >Jeff? I guess this will be the behavior of P32 anyway, since RET does
> >not occupy a whole instruction slot.
>
> This is not the case on F21. In MuP21 or F21 if you execute a RET (;)
> it is the last instruction you execute in that word.
Since I know nothing of the actual design, my speculations are just that
-- speculations.
I see only one reason why RET should scrap all slots after it. This is if
starting RET earlier accelerates the beginning of the next memory fetch.
If the next memory fetch cannot be accelerated, I see no reason (other
than possible design simplicity) why ALU instructions (including NOPs)
could not execute after the RET. This setup will have to assume, that no
memory references ( A/R @/! ) nor return stack manipulations appear after
the RET.
On the other hand, the only useful instruction to appear after the RET as
opposed to before it, is a + . I don't know how frequently will this be
useful, but I can envision some index calculations, that will end in a + ,
and in _some_ cases will save an instruction fetch.
> You are right about P32 where there will be a one bit RET instruction.
> I don't know if that means that Chuck will replace the normal RET
> instruction with something else.
There are unassigned instruction codes in MuP21 and F21. Maybe there will
be one more in P32 :-)
--
Penio Penev <Penev@venezia.Rockefeller.edu> 1-212-327-7423
