F21_stacks

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear MISC readers,

Penio Penev asks:

>> I have been testing F21 in the OKAD simulator.  F21 has an array of
>> 16 stack registers that are circular.  
>
>Does the circularity serve any design goal, or is it a by-product of other
>design decisions? 

Chuck and I did discuss this last year.  The circular stack was the easiest
way to extend the stack to the current size.  The circularity was one of
the options.  It seemed like it might have some usefullness, but it is
basically just one way to do it.

>I wold suppose that the stack elements are laid out linearly, with S0
>very far from S16. Now, to achieve circularity, one has to run wires all
>the way up to connect them. Is there any reason for doing so?

I think Chuck chose this approach to minimize hardware.  There are fewer
lines and connects this way than any other way we could think of.  

Wires run all the way up and donw the chip, they have to.   The bits are
arranged in columns.  This is one of the characteristics of the MISC
designs, and it what makes it so easy to scale them from 21 to say 32
bits.

Control logic is on the right side of the chip, just to the left of this
is bit 0, then bit 1 etc.  The left side of the chip is carry.  A vertical
wire must carry each bit to all coprocessors, data and return stack
registers, and alu logic.  So there are many vertical wires running the
length of the chip.  The fact that 1/6 of the length of these wires
runs accross the stack arrays is not an issue.

Chuck uses a sort of pointer ( a 16 bit circular shift register ) to
designate the current location being used in the stack array.  Data is
copied to or from the N register and stack array according to this
pointer.  It looks to me like a LIFO buffer would take twice as much
logic as this approach and would draw much more power.  The minimal
way to do it is just to read/write one stack location in the array,
and shift the pointer up or down.

The real issue is whether the CPU and read the stack pointer shift
register.  It is unfortunately not readable  by the CPU in F21.  So
there is no hardware way to determine the current stack depth.  Nor
can you reset it except by cpu reset.

To determine stack depth you need to maintain a counter in memory,
but this would add a great deal of overhead to execution speed.  A 
DUP will only take a few ns, but incrementing a counter in memory
is very slow since it takes a couple of memory accesses.

What I intend to do is fill the stacks with a known pattern at boot,
and when you need to determine stack depth, flush it to memory and
examine it.  You would not have to do this if the stack array pointer
was an addressable register that the CPU could read, and it was not
circular.

But MuP21 had only 1 addressable register, the configuration register.
F21 already has a half dozen new addressable configuration registers.
It seems we are now up to about 15k transistors on F21.  Chuck has 
complained that he has really added too much new stuff as it is.
If we had a budget we could submit more designs with fewer changes to
each design.  F21 has already become about 10x the complexity of P21,
considering 5 processors instead of 3, three sources of interrupts,
deeper stacks, new instructions, new branching modes, more pins, etc,
you have to draw the line somewhere and say "lets try this out."

Jeff Fox