MeshSP vs. P21

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

Penio Penev says:
> While the unit is not MISC, one can see where the alternative solutions stand
> at the moment.

I don't think it is an alternative.

MeshSP is built with an array of Analog Device's ADSP-21060 SHARC (Super
Harvard ARChitecture).  The SHARC is a huge piece of silicon running at 40MHz,
with:
- pipelined one-cycle ALU/multiplier/shifter for 32bits fixed-point or IEEE
  32-bit floating-point or extended precision 40-bit floating-point processing
- a 10-ported (yes, ten) register file of 32 registers 40bits each
- an instruction cache for 32 instructions (instructions are 48bits wide)
- 2 independent Address+Data memory buses, one 24+48bits, one 32+40bits
- 2 Data-Address-Generators with 32 address registers and circular addressing
- 4Mbit on-chip SRAM, as 2 independent 2Mbit banks each dual ported and
  allowing 16/32/48 bit accesses
- 4 Gigaword off-chip address space with memory-bank select predecoding, DRAM
  page access support, multiprocessor arbitration support and host-processor
  interface support for external vectored interrupts
- a DMA controller supporting 10 channels
- 2 synchronous bit-serial comports, 6 data+control lines each, 5Mbytes/s max
  throughput each
- 6 asynchronous nibble-serial comports, 4 data lines and 2 control lines each,
  40Mbytes/s max throughput each
- a JTAG test access port

Only for the on-chip SRAM, at 6 transistors per bit, there are 24Mtransistors.
I'd like to see the size of the die ... and its yield and price.

The SHARC is an alternative to other Digital Signal Processors (DSP) such as
TI's TMS320C40, or to high power general purpose processors such as DEC's Alpha
or maybe Intel's P6.

The P21 is not an alternative to such monsters.  It's not designed for number
crunching as are DSPs.  It's a few Ktransistors, a few millimeters square, a
few milliwatts, but a few dollars (in production quantity) for several hundred
Mips (the F21 is expected around 300Mips and 500 to 800Mips may be expected
with .5 or .35 micron processes).

A comparison between the P21 and other processors will be possible only through
specific applications.  The P21 is small enough a design to allow small/medium
companies to integrate on the same chip a fast core with specific I/Os at low
cost.  It's well suited for instance for video processing consumer products,
because its speed together with an integrated monochrome A/D converter allows
video-processing on the fly without the need for an expensive frame grabber,
required for other processors to cope with 5 or 10MHz pixel rates.

email: Christophe.Lavarenne@inria.fr		tel: +33(1)39.63.55.80
INRIA, Domaine de Voluceau Rocquencourt		Institut National de Recherche
B.P.105 - 78153 LE CHESNAY CEDEX FRANCE		en Informatique et Automatique