Parallel-MISC

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear MISC readers,

Eugene wrote about MISC chips:

>I'd even wish for 5-10 all purpose registers, though this would bloat
>code space and disable multiple instructions in single word feature.
>Home code page in SRAM can possibly alleviate the lack of generic
>registers.

I think you could get what you want without much penalty.  The
SRAM home page access is nice, but it is still external memory and
requires a set up time.  Even with the smallest setup time and
fastest ram easily available an access to external ram takes the
same time as about 4 instruction clocks.  Addressable register
access still goes through the memory processor I think, but it
could be set to take only about two clock cylces.  Of course their
are instructions that access the A and stack registers in one
cycle because no addressing is involved.

There are also five unassigned (memory access) opcodes in the
instruction set.  If these instructions are used you could make
one a five bit argument with two cycle register access, and
many some other opcodes for one cycle access like A@ and A!. 
Of course someone would have to pay Chuck to add new opcodes and
add registers.  Registers are also expensive in the sense that they
are the biggest visible portion of the layout.  In other words 32
registers alone would require about 50% more silicon, and the extra
instruction decode and execute would add a little more to the alu
section.  It might be just the feature that is needed to make it
programmable easily with C technology.  If it doubles the price of
the die to do this it would be a small price to pay.  F21 might
cost slightly over $1 to manufacture in large volume with this
feature added.

I like to think up new instructions like that and try to figure
out what the design tradeoffs will be, then discuss it with Chuck
and see how close I was to what thinks he would have to do.
More memory access via different registers could also be added.

You could think of these general purpose registers as on chip sram,
but since you could have special instructions like A@ you could
access some of them somehow with addressing already set up in
hardware so that it happens in one instruction cycle.  If you
use 5 to 15 bit type address to get at the registers I think 
it takes a minium of two cycles for instruction execution and
then access.  I am not sure but I think the way the instructions
interact with the memory processor in the current design the
A@ is once cycle because it is not memory access, and @A or @A+
_could_ execute in two cycles if the address is decoded on chip.

I imagine it would make things much more complex if you try to
make these (on chip sram) registers also act as memory addressing
registers.  That might be quite involved, I will cc Chuck on that.
Like some on chip sram, general purpose registers that can act
as pointers to memory are powerful.  It would be great if the
MISC approach can deliver useful register (on chip sram or whatever)
access in a conventional way more or less to compilers, but
without the conventional penalty of large instructions.

Of course F21 will not get any major changes like this.  It will
get bug fixes, and _maybe_ implement something on the two unused
pins on the first prototype.  But Chuck will be making more chips.
I expect he will do a 64 bit with multiple high speed serial links
and on chip sram and at rediculous speed before long.  He is now
dealling with the .8 to .5 micron jump as the results from .8
prototype runs comes back.  It won't be that long before he makes
the next step to .35.  At that point he can do very small chips
with lots of pins and a gig cpu throughput, multi-giga serial
( or parallel) links, and lots of 1 or 2 ns access registers.
The smaller faster geometry makes everything except pins pretty
cheap, and pins are not expensive.

This place seems like a good forum to discuss this sort of
thing.

Jeff Fox