Re: P64 Math

[Steve Atkins <atkinss@xxxxxxxxxxxxxx>]

>>Readers,
>>
>>The hypothetical "P64" design has been mentioned several times here.  I'm 
>>curious whether 64 bit-wide math would require some different approaches in 
>>terms of silicon.  Specifically, the carry propogation of the P21 limits how 
>>fast a program can perform successive additions or multiply steps.  F21 will 
>>have similar constraints from what I've seen.  Will the planned P32 use an adder
>>with ripple carry?  Is there a limit to how wide it is reasonable to use such an
>>adder?  Maybe 32 and 64 bit designs will require the much more complex carry 
>>prediction silicon in order to get acceptable performance.

When you hit 32 bits I think it's worthwhile to use some sort of carry
propagate acceleration. Something like a carry skip adder doesn't cost too
much silicon, and will be *much* faster than a ripple adder for wide words.

I've been looking at 64 bit arithmetic recently, and (for the silicon we use)
the tradeoffs do seem to change between 32 & 64 bit operations. For a fast 64
bit processor, where addition may be a bottleneck, a good optimised adder would
be essential - either a carry skip adder for medium speeds, a hybrid carry select
adder (such as the one the Alpha uses) for fast speeds. If the word width grew
beyond 64 bits, or *very* fast addition was the aim then bizarre adder
architectures (Prefix adders, such as Brent-Kunge or Kogge-Stone (sp?)) start
looking like a good idea. They're pretty expensive on silicon, unfortunately.

Cheers,
  Steve
--
-- Steve Atkins -- <atkinss@inmos.co.uk> -- +44 454 611439 --
--            http://pact.srf.ac.uk/~atkinss/              --
"At least one good reason for studying multiplication and division is that
 there is an infinite number of ways of performing these operations and hence
 an infinite number of Ph.Ds (or expenses-paid visits to conferences in the
 USA) to be won from inventing new forms of multiplier."
                   -- Alan Clements, The Principles of Computer Hardware, 1986