No Subject

[jfox@xxxxxxxxxx (Jeff Fox)]

>From: Penio Penev <penev@pisa.rockefeller.edu>
>Subject: Re: news
>
>On Thu, 28 Dec 1995, Jeff Fox wrote:
>> A second F21 was sent to MOSIS last week as was the first I21 prototype.
>
>What is an I21?

i21 is the custom processor for the iTv Corporation.  It is a proprietary
chip for a product and will not be available as a chip to the public.

>> This F21 has four of the five know problems fixed.
>
>This is actually the first news in MISC about the results of the first
>F21 prototype. It's good to know, that the problems were fixed, even
>though we never knew what they were :-)

Six actually I guess:

1. Composite video output not connected (ntsc encoder not completed)
2. T.10-T.19 shorted to data bus
3. Analog coprocessor clock permanently enabled by short
4. Parallel port short
5. Instruction sequencing problem
6. Memory timing off by 10x

Bugs 2 through 4 were shorts between circuits that were not detected by the
simulator.   These shorts were visible in the design to the eye when
you knew what you were looking for.  Scanning the design for these
types of errors found only a few.

These errors were due to a problem with the way Chuck represents rectangles
in his tile system.  When you look at the geometric representation of the
design you can see that the poly regions expand to fill in the areas between
tiles so that poly makes nice filled in areas.  But at other times poly
is the line of conduction so if two different poly lines are on adjacent
tiles they are shorted.  If they are in different circuits they should
should not look like that and the simulator does not catch it.  Searching
the chip visually in the simulator for this problem was quite interesting.

As for each of these problems:

1. Composite video output not connected (ntsc encoder not completed)

Chuck never finished the ntsc encoder because he was in the process of
redesigning it.  He didn't like the quadrature composite video encoder
because it introduced too much noise in higher harmonics.  This resulted
in some colors that are hard to use for anything in MuP21.  But Chuck
has been trying some different things on other chips and just has not
put a composite video encoder into F21 yet.  The RGB and composite outputs
run at the same time anyway.  It is a specialized D/A with RGB outputs and
some form of encoded composite version of the RGBi signal on the yet to
be completed on F21 composite video output line.

2. T.10-T.19 shorted to data bus

The problem was found by Chuck and identified as a design problem about
the time the F21 was submitted to MOSIS.  I could have canceled the
fab run since it had only started, but we knew that the 10 top bits on
the data bus were permanently shorted to the T register.  This limited
my expectations to testing the thing in 8 bit instruction mode if it
was going to work that well.

3. Analog coprocessor clock permanently enabled by short

I didn't see this one, but Chuck said that the short in the circuit
from the analog coprocessor count down clock was permanently
enabled on the bus.  After 300ms of operation the analog coprocessor
would start reading and writing on the data bus and no more access
for the CPU would occur.  The address and data bus would just show
this steady pattern.  All testing had to be done with short programs
that executed while the cpu had control and the results examined
post mortim on a logic analyzer.

4. Parallel port short

One more short not apparent from testing in the OKAD simulator.  These
were simply human errors in the design layout.  The port had been tested
in the simulator but did not work properly.

5. Instruction sequencing problem

Chuck reported that you could not get a memory access instruction after
a jump instruction due to an internal ALU/CPU/Memory interface internal
sequencing problem in the design.

6. Memory timing off by 10x

Chuck tried a whole new way of timing the memory interface.  He make it
programmable and it worked, but he was off on one estimate and it charged
up this timer about 10x slow.  These curves get pretty flat pretty fast
and he hit it too low.  The cad system uses an innovative approach of
simulating the analog operation of the entire chip.  Chuck has changed
from voltage simulation to current integration simulation in the latest
OKAD.  This allows more accurate simulation of slowly changing analog
processes in the OKAD simulator.  I expect F21b should be closer to the
corrent timing mark.

In addition to these known problems there were also some future "tweaks"
that were planned for the second prototype but were not done on F21b
because they involve results from more detailed testing of I/O
coprocessors than was possible with the first prototype.  I would like
to be able to run the serial network as fast as the design will
support and this will require tweaking because Chuck has not done these
high speed serial signals yet.

A third prototype will be done.  If production is done by MOSIS
the price will be higher, but if it moves offshore then another
prototype will be done.

>Any news on F21 boards?

No not really.  We have only had wire wrapped boards for the testing we
have done on F21.  It was on my list, but budgets and priorities.  At
least I have more experience with the way the various chips connect and
the things Chuck wants to do better testing next time.  Besides a nice
quite board, (I think 4 layer is needed for clean first testing) things
link vias for jumpers to all the power and ground leads to the processor
so that 1 ohm resistors can be substituted for jumpers on these leads
for examination on a scope.

I got various suggestions about boards from people and the information
was helpful.  I am about to start a new design for a prototype chip testing.
I still do not have a conventional CAD system to do the thing but I
figure if I did, and new how to use it that it could not take much
longer than it does to wire wrap the thing and that only takes a couple
of hours.  The wiring is very simple, it connects directly to some ram/rom
and F21b testing will be done on a simple board with a few extra jumpers
added to facilitate testing, otherwise Chuck would like it as small
and clean as possible.

I got a couple of future volunteers last time, but I don't know if anyone
else will get involved in this test board.  I need to get moving because
F21b should be back before the end of February.  I know I can get boards
made in a few days.

Jeff Fox