Re: Misc instruction sets

["Robert J. Brown" <rj@xxxxxxxxxxxxxx>]

>>>>> "Wayne" == Wayne Morellini <waynem1@cq-pan.cqu.edu.au> writes:

    Wayne> From: "Robert J. Brown" <rj@eli.wariat.org>
    >>>>>>> "Wayne" == Wayne Morellini <waynem1@cq-pan.cqu.edu.au>
    >>>>>>> writes:

    Wayne> Yes and they are also run on common office programs.  What
    Wayne> I am looking at is what is needed in most areas, and
    Wayne> provide a miniumalist set of words to archieve it, ie look
    Wayne> at Chucks innovation of the Address register in Mup to
    Wayne> consecuvately reference memory locations, how much time
    Wayne> does it save over having the adress on the stack etc.  Any
    Wayne> help on this endeavour from anybody out there would be most
    Wayne> appreciated.

A friend of mine and I started designing a processor, which we stopped
work on (suspended tmporarily?) because of the availability of John's
design.  We are on a schedule.  We looked at both MIPS and ARM, but
the foundries are not really quite ready to divulge final details on
these engines yet, as they have never actually used them except on
inhouse projects.  We need a CPU now!

This processor we started designing is called FISH (Forth In Silicon
Hardware) and has multiple parallel memory systems, taking advantage
of on-chip memories.  The instruction memory is ROM.  The data memory
is RAM.  The parameter and return stacks are each in separate RAM.
There is also a novel loop stack with return address tagging that
permits iteration of both hardware instructions and threaded words.
Nested loops are supported by automatic stacking.  The is also a
hardware leave instruction that exits the innermost loop.  This
looping hardware was to be used with a fast vector dot product ALU
that would take a vector of constant integer coefficients and dot them
with a vector of variables.  The constants would be in instruction
ROM, and the variable vactor would be in data RAM.  This would permit
the formation of one multiply and add term of the dot product per
memory cycle -- very useful in signal processing applications.

Then, of course, there is my pet project: MOOSE (Machine for Object
Oriented Software Execution).  MOOSE is a hardware architecture
optimized for fast context switching and non-local exits in a
dynamically bound object oriented environment.  For a glimpse at some
of its features, see:

    http://eli.wariat.org/~rj/dreams/dreams-rep.html

-- 
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Robert Jay Brown III  rj@eli.wariat.org  http://eli.wariat.org  1 847 705-0370
Elijah Laboratories Inc;  759 Independence Drive;  Suite 5;  Palatine IL 60074
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