MISC

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear MISC readers:

Andrew asked a few questions:

>- is the MuP21 kit stand-alone? (Meaning, can I just hook up a standard 
>  PC keyboard and a (NTSC/PAL) CRT to it and use it for native 
>  development platform?)

That is the idea.

>- what does it use for mass storage? Flash memory cards?
>
>- can one use the digital I/O ports to do several RS232 by software?

Yes, but if you bit-bang timing drift can be a problem.  One solution
I used for one client was to put a stable timing signal on one of the
pins on the parallel port and read it to get the bit timing on the
serial interface.  We were able to run several serial ports at different
baud rates up to 115kb quite reliably.

>- is the only difference between the $100 and the $350 kit is that the 
>  latter is assembled? (Meaning, containing the same parts, identical 
>  documentation and ROM image?)

I think the rom image is slightly different because the i/o addresses
may not be the same on the two boards.  but  I don't know for sure because
I haven't seen the new board and documentation yet.

I don't know what comes with each product.  Some users have complained
that they expected a manual with the kit and found they had to order one
separately.  There were several versions of documentation distributed
without release numbers and I know of several inaccuracies in each
version that I saw.  I would be careful about finding which documents
come with which product.

When I made arrangements with Dr. Ting to distribute P21Forth my
understanding was that he would include a ROM, cable, manual and
diskette.  Instead people got a printed manual and diskette only,
and the first version didn't even have a ROM image on the
diskette let alone a ROM.

>> for, the Mup-21 execution has been reported to break after something like
>> 100's of hours, but new packaging that was due soon this time last year and
>
>What??? You mean all MuP21 samples one can buy are uncapable of sustained 
>operation???
>
>Can somebody please confirm this observation?

I have had P21 running tests for days on end.  I had one test with one
task doing a computation, another task checking it, and a third task
counting the task changes.  I ran it for days without problems, through
tens of billions of task changes.

On the other hand if you are bit banging serial i/o without a timing
source you can easily get out of spec before you can download a big
application from the PC.

>I'm still not sure I've figured out why NOP gives the ability to save
>power.  It seems to me that all you can do is lower operating voltage
>to save power.  NOPs do nothing to save power, as far as I can see.

NOPs don't save power.  You can also save power by not generating
video, or generating black instead of white.   White draws more
power on the video pin than black, the analog video output on P21
is where you find the biggest power transistors on the chip.


>The inversion of odd address and data bits is rather confusing.  If
>I were to add inverters to the odd address pins and two-way inverters
>to the odd data pins, then would ALL of the inversion mess go away?
>Would I be able to program it and never have to XOR anything with
>AAAAA or worry about the inversion stuff at all?

I doubt it.  First of all you circuit will load the bus, then also
your circuit will require time and will slow the timing between
P21 and memory.  You might get it to work, and yes if you inverted
even bits on the address and data busses then a 1 on MuP21 would
look like a 1 on the PC.

But I find the idea very strange.  I just can't imagine modifying
a computer bus so that I could remove two instructions somewhere
in my development software and end up with a unique set of hardware
and software that would require conversion to run on any other
machine in the world.

This is no different than your telling me that you want to put
inverters on all the bits on the data bus of your new computer
because it has a postive logic bus and your last computer had
a negative logic bus.  So to port your software you could
use software to invert all the literal data in your program,
or you could design and install something to intercept and
invert the data signals on the bus.

I find it so strange because it is just a matter of perspective.
I you have an 8 bit computer do you really care if it represents
a logical 1 on the bus with a 5v or a 0v?  It will be totally
transparent from the logical operation of the cpu.  But if you
burn a prom and then place it into a computer with the opposite
type of bus guess what?  The same data will now appear inverted.

So which is correct Postive logic, Negative logic, or the complementary
bit logic that Chuck uses on P21?  Well each is just as valid as the
other.  We don't have clay tablets from GOD saying that a computer
must represent a logical 1 with a +5v on the bus.  If we did then
a lot of computers that use negative logic representation on the
bus could be thought of as "wrong".

Does it confuse you that the same ROM will read differently on
different computers?  It really isn't that complicated.  Now I
will admit that xoring the address and data bus with AAAAA is
a little more complex than xoring the data bus with FFFF but
not much.

What makes it confusing is that each time you apply the AAAAA XOR
you are switching from number to pattern perspective, and if you
do it two times you are back where you started.

When you work with CAD system or with a logic analyzer on a MISC
chip you must xor with AAAAA for the data to make sense.  When
you see AAAAA AAAAB AAAA8 on the data bus you know that is
0 1 2 to the MISC processor.  Chuck tends to use this perspective
because he must deal with the voltage level on each wire in the
CAD system.

If you cross compile (or target compile) for a MISC processor from
a different machine then you must also XOR addresses and data
so it will look the same when it gets to the target machine.  It
really is not complicated, I can't imagine trying to modify the
hardware to mask it.

>If I use the fast I/O space for 15ns sram hookup, and run a program
>out of it (I know the program would have to be <1k), will the
>program run faster, since it does not have to access relatively
>slow dram?

Yes, if you use cache ram chips you can get 40ns access in SRAM
(15ns chip access and 25ns P21 memory setup time) which is faster
the the ~50ns needed for on-page DRAM.  But this is REALLY faster
than the ~150ns off-page DRAM access time.

>If these issues have already been covered in this mailing list and
>they're stored in the archive, I've had no time lately to read
>them, so I apologize if these are repeat questions.
>
>--Andrew Sieber
>kd4jtv@bbs.wa4yse.ampr.org

Jeff Fox

jeff@itvcorp.com       the iTV Corporation
jfox@netcom.com        Ultra Technology Inc.
jfox@dnai.com
http://www.dnai.com/~jfox