Re: bits, timings, mem maps, etc.
On Fri, 11 Oct 1996, Christophe Lavarenne wrote:
> Then in the best case, where none of the 4 instructions references memory, the
> next instruction word is fetched in parallel with the execution of the 4 instr,
> which are executed faster than the memory access, this is why a + in the 4th
> slot does not require a nop in the 1st slot of the next instruction word,
> because there is time after the + to propagate the carry before the next
> instruction word is loaded and the 1st instruction slot is executed.
The greatness of Chuck is in part in his thinking in non-stereotyped ways.
The particular stereotype that he broke and tokk me quite a while to get
is that you first decode instuctions, then execute them. This is not the
case with the non-memory-access instructions in x21.
Since there are very few posiible instructions to execute, x21 executes
them all in parallel, producing the resluts of all of them in internal
registers. The decoding of the intruction merely tell you _which one_ of
those internal registers to latch to TOS. Therefore, the adder gets
started the moment the stack contents get changed and runs freely,
propagating carries, at all times. This means the the delay is done with a
NOP +, versus a + NOP. This means that a + does not need a NOP if it is
in the _first_ slot, _and_ you don't execute from SRAM.
A discussion about how things are done is avaible in the archive -- look
for "Sequencing of instructions".
This is most definitely a FAQ. I can get the (20 or so) posts that
discuss it, formulate the questions, write the answers, submit them to
Jeff for final check and put it up-front.
--
Penio Penev <Penev@pisa.Rockefeller.edu> 1-212-327-7423
