speed & schematics

[Andrew Sieber <kd4jtv@xxxxxxxxxxxxxxxxxxx>]

Christophe Lavarenne wrote:
>>the processor must still load operands from memory every fifth cycle, it
>>seems to me that even with 15 PICOsecond sram chips the processor would
>>still only run at 80 MIPS.
>There is no fifth cycle.
>The next instruction word is prefetched as soon as possible.

I didn't realize the MuP21 had a 20-bit instruction "cache" for the next
word that is loaded while the current word is still executing.  If it
loads while the current word is executing, it'd have to have one,
otherwise
it'd overwrite the instructions currently being executed.
So with sufficiently fast SRAM (like 15ns?), and only ALU and register
instructions (other than addition instructions), the MuP21 can in fact
be made to run at 100 MIPS?

>MIPS has never been a good performance scale to compare processors, and in the
>case of miscs it's worse, because the instruction set is so different and
>instruction timing depend on voltage and on memory addresses.

I realize this; it might take half a dozen MISC instructions to perform
the equivalent task of one CISC instruction.

As I understand it, the MuP21 can run at 104MHz.  I also understand that
this clock speed varies slightly based on the supply voltage.  What are
the minimum and maximum operating frequencies?

I just received all the parts I need from Jameco, and I'm going to build
a system, sans PCMCIA, using the schematic on page 92 of the
Programming Manual, 3rd ed.  But it doesn't show how to hook a standard
PC keyboard to it.  How do I do this?  And for my EPROM chip, should I
use the SLOW.ROM image file of P21Forth 1.02, or FAST.ROM ?

--Andrew