No Subject
- To: MISC
- From: jfox@xxxxxxxxxx (Jeff Fox)
- Date: Sun, 17 Nov 1996 02:44:58 -0800
Dear MISC readers:
Andew asked:
>what is intended. Am I reading the schematic wrong, or is
>it
>backwards? I'd like to know before I build a system, else
>I
>might destroy my MuP21 when it and the '245 fight for
>control
>of the bus. I haven't done an exhaustive search, but I did do
>a quick check through the MISC archives and didn't notice
>anything on this topic. Any clarification would be appreciated.
>--Andrew Sieber
>kd4jtv@bbs.wa4yse.ampr.org
I don't recall exactly how his circuit worked, but I think
he cheated on the output latch. The part wanted a positive
going pulse while P21 provided a negative pulse but it
sort of worked by latching the wrong side of the pulse
anyway so Dr. Ting used the part.
I used different parts when I designed a substitute arrangement
for the orignal parallel i/o chip on the original development
system. I know I showed the circuit diagram that I used one
time here in MISC. It made more sense to me than Dr. Ting's.
It is pretty straight forward to design i/o on P21. The pin
labeled i/o is really sram select. The sram address space
is one place to decode memory addressed i/o. You use the
i/o pin and some address bits and write enable to select
and decode input or output latching of the bus.
Don't worry about frying P21 it is very tough. I have
wired up the 5V backwards and heated the chips up to well
past 100C and haven't fried a P21 yet. I have even tried.
Jeff