questions

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear MISC readers:

Francois-Rene Rideau <rideau@ens.fr> wrote:

>Also, I'm looking for a simple semi-portable FORTH-like virtual machine
>that I could use as an interoperable implemention of my OS.
>I think the F21 instruction set is too basic for that.
>What do you suggest?

Nothing right now, but I am working on something.

>P.S.: a few questions about MISC chips:
> 1) *what?* if I don't wait enough time for the carry to propagate before +?
>  What can I predict about the result?
>  Can it be used when I know the carry won't propagate,
>  or specifically want it not to propagate to much?

If you don't provide enough time for carry the result of the add
will not be correct.  But as you can see 1FFC00 3FF + has no carry
and happens in 2ns.  Carry will only move 2 or 3 bits in the time
the + instruction executes.  Nops only provide 2ns each or time for
2 or 3 bits each.  In DRAM it is always safe to use + as the first
opcode in a word because the 40 - 150ns time to load the instruction
provides plenty of time for the correct result.  + and XOR will 
provide the same result for operations where these is no carry.
To predict the result just move the carry from the least signifigant
bit where it starts at about 1 bit per ns to see the intermediate
result at any particular time.

To count a loop 100 times Chuck uses left justfied numbers to
reduce carry requirements.  ie start with 0, use 1000 as the
increment and add it 100 times to get carry (100000).  Chuck
would use a -IF or -UNTIL to test for carry.  You might be
able to save a few nanoseconds this way.

> 2) how does the F21 translate stuff from 8-bit boot ROM
>  into 20-bit instructions?

The P21, F21, i21, etc all have 8 bit wide and 20 bit wide
address spaces.  They boot in 8 bit wide space.  In this space
only the last 5 bits  contain an opcode so the processor only
executes the last five bits.  DUP DUP XOR still generates a
21 bit 0 in T and DUP DUP COM XOR still generates a 21 bit -1 
in T but it takes four bytes of opcode in 8 bit space.
So far MISC chips have done very little in 8 bit space
except boot code to dram and set the memory configuration register.
There have been some simple application programs written for ROM
and yes a ROM and a P21 is all you need for some things.  But
with 250ns (or even 150ns) access and only 8 bit wide space
it is very slow.  
These chips also have a slow and fast 20 bit space that can also
support ROM or RAM.  It is used for I/O space on Dr. Ting's
boards.  One could put 16 or 24 bits of ROM into that space an
read 16 or 20 bits of data.  You could not execute instructions
out of that space with only 16 bit wide memory since the upper
four bits would not contain anything.

The # opcode however will only read 8 bits from an 8 bit 
wide ROM.  So 20 or 21 bit numbers must be loaded by
several # opcodes and combined, or constructed with other
math operations like COM 2* + etc.  The assembler can
provide support so that for code that executes from 8 bit
space n # would compile to one opcode if n is 8bits or less
and would compile a longer sequence with two or three data
loads or some math if needed.

> 3) how do you use the +* operator?
>  it looks like to me it is complicated to use,
>  and eats up the low bit as a flag during multiplies;
>  what is an actual multiply routine like?
>  Say sources for UM* ?

+* was designed for 9x9 bit multiplies in OKAD.  It is very good for
that, and Dr. Montvelishsky has used it in a number of math words
to get a few nanoseconds there and there.

It is the same as
: +* ( n1 n2 -- n1 n2 | n1 n3)
 DUP 1 AND 
 IF OVER + THEN
;

ie it is a multiply step as in

\ 4x4* example ( n1 n2 -- n1*n2 )
 PUSH ( >R)
 2* 2* 2* 2*       \ shift Second item 4 times
 POP ( R>) *+ 2/   \ there can be no carry on the first *+
 +* 2/ nop nop
 +* 2/ nop nop
 +* 2/ push drop
 pop

This adds the pre-shifted argument in S conditionally on bits in T
and shifts through the bits.  It works on things up to 9x9 but
you can't do this on double numbers.

> 4) when is the P32 scheduled for?
>  Will it have a 32-bit or 33-bit ALU?

> 5) Is there any project for MISC
>  technology to be used in PC-class and/or laptop/handheld computers?
> I'd love a cheap voice-driven portable computer system,
> with optional LCD interface and desktop computer connectivity!

>== Fare' -- rideau@ens.fr -- Franc,ois-Rene' Rideau -- DDa(.ng-Vu~ Ba^n ==
>Join the TUNES project for a computing system based on computing freedom !
>                TUNES is a Useful, Not Expedient System
>URL: "http://www.eleves.ens.fr:8080/home/rideau/Tunes/";

There were two P32 being developed at one time. One for use in a PDA
and one for a router.  The future of these chips is not clear.

iTV does have plans for future chips including 32 bit designs with
on chip memory etc.  The details are not public yet.

Jeff Fox