RAM on the chip

[Penio Penev <penev@xxxxxxx>]

On Thu, 13 Mar 1997, Jeff Fox wrote:

> As Chuck has said before he is not good at designing ram and it is very
> expensive to put it on a cpu.  

My point was, there is unsused area on the chip anyway, so (aside from
development costs and lower yields) there is no additional price to be
paid for the additional RAM. 

> F21 has 18 data stack registers, 17 return stack registers, 2 control
> registers for video, 4 control registers for network, 1 analog control
> register, 1 memory access control register, 1 parallel port control
> register and a few internal control registers.  The 35 stack registers
> take up about 50% of the die that is used on the chip.  And based on
> that size it might be possible to add that many registers decoded
> as on chip sram locations.  

35 words, four instructions each is not much, but a convolution kernel, or
a dot product kernel, could definitely fit in there. 

> However at the present time these chips
> produce the same timing for access to these registers as they do to
> high speed sram.  So just putting them on the chip doesn't give you
> anything unless you provide a faster path also to on chip memory.

Well, it does.  It allows you to build a system that is capable of 180
MIPs (4/22ns) _without_ external SRAM (which is a few dollars), thereby
reducing th chip count and price.

Of course, it would be great if the bandwidth to this memory was really
fast.  I.e., the SRAM speed register could accept values for something
like 2ns (500MHz). Unfortunately the 10ns setup would stay, thus giving
330 MIPs (4/12ns).

What is involved in making the internal memory perform fast?

> I would estimate that the design time, and the time for additional fab
> runs to debug a chip with on board ram would add between six months to
> a year to development time.  F21 design was paid for at a lower rate than
> what Chuck would charge now, so a substantial redesign to F21 would be
> expensive at this time.

Aha.

> 
> Bottlenecks?  Well design time, 2 month fab delay, about 1 month typical
> testing, and redesign means there is a 3 or 4 month delay in the development
> process.  

So, practically when one submits a design, he has a chance to submit the
revisions based on the tesing of the result in 3 months.  And another 3 to
get them back, that is 6 months if the first design is basically there,
and only a second one is needed to verify that the errors are ironed out. 


--
Penio Penev <Penev@pisa.Rockefeller.edu> 1-212-327-7423