Re: RTX2000 successor question

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

Ray Gardiner wrote:
> We have been using the RTX2000 for a number of years in a real time imaging
> system, and are now starting to look about for a suitable successor.
> ...
> Has anyone had experience with moving from RTX based applications to P21?
> Are there other choices I should consider?

It all depends on the kind of application you are targetting and when you want
to do it.  P21 is available now, from Ting.  F21 will be more powerfull, but
it's not yet available.

We are developping the v21 with Chuck, with an integrated video input, for low
cost (and low resolution) embedded real time video processing.  But it won't be
available in a near future.

For another application presently based on a multi-RTX (two RTX2000 per PC/ISA
board), we are moving to a multi-SHARC architecture (six ADSP21060 per PC/PCI
board).  The SHARC (http://www.analog.com) is a floating-point DSP as
predictable as the RTX, with a 25ns (40 Mips) instruction cycle time,
integrates 4 Mbits of dual-port on-chip SRAM, six 4bits-parallel 40Mbytes/sec
interprocessor communication links, 2 serial links, a 32bits/Addr 48bits/data
shared bus with integrated arbitration including for a host, and a DMA engine
to serve all these interfaces.  Forth-like interactive incremental compilation
is easy to implement thanks to its host interface which lets the host access
all SHARC internal ressources, including interrupt triggering.  It's fun.

At the INRIA, we are developping the "Algorithm/Architecture/Adequation"
methodology and the SynDEx CAD software which supports it, to optimize the
implementation of image and signal processing and control algorithms on
multicomponent architectures for real time embedded applications.  The user
interacts with SynDEx to specify and characterize his algorithm and his
architecture, then to find the best distribution and scheduling of the
algorithm operations on the target processors, and finally automatically
generates the minimal executive which supports the distributed execution of the
algorithm on the architecture, thus saving the burden and cost of writing and
debugging it.

The future of the v21 will be to integrate on-chip memory and programmable DMAs
to manage, with minimal silicon and high predictability, input/output transfers
including I/O data streams, transfers between the internal memory and external
memories, and interprocessor communications.

Christophe
--
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INRIA, Domaine de Voluceau Rocquencourt		Institut National de Recherche
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