80 MIPS peak?

[Penio Penev <penev@xxxxxxx>]

Dear MISC gurus,

I am trying to achieve the 80 MIPS peak, advertized on page 1 (and
elsewhere) in Dr. Ting's MuP21 Programming Manual. 

The second sentence of the second paragraph on page one reads "20-bit
words are fetched from the DRAM memory at a rate of 20 MHZ.  Each word
contains four 5-bit instructions, and the sustained [ I guess peak is a
better word ] execution rate is 80 MIPS." 

Then, we go ahead and the following experiment:

CODE T1
a push nop push
DECIMAL 1000000 # nop nop nop
begin
while
  dup dup -or com 
  + 
repeat

pop pop nop a!
@+ push ;'
END-CODE

CODE T2
a push nop push
DECIMAL 1000000 # nop nop nop
begin
while
  dup dup -or com 
  nop nop nop nop
  + 
repeat
pop pop nop a!
@+ push ;'
END-CODE

The difference is 1 milion "nop nop nop nop"-s.

Then we do:

: 50T1 50 FOR T1 NEXT ;
: 50T2 50 FOR T2 NEXT ;

50T1 executes for 24 s, against 32 s for 50T2:

These are 8G ns for 50M "nop nop nop nop", which is about 160ns for
instruction -- roughly 125% * 115ns (ajusting for video bandwidth). 

This is suspiciously close to 50ns (RAS time) + 25ns (setup time) + 40ns
(execution time).  I.e., the peak rate of memory access is 9MHz, not 20,
as indicated.

Am I completely at loss?

I think Jeff once mentioned that the next instruction prefetch begins as
soon as there is no pending memory instructions, therefore the 40 ns of
"nop nop nop nop" should be entirely overlapped with instruction prefetch,
be it 50ns + 25ns.