Re: P21 Boot Help (fwd)

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

   Date: Wed, 9 Apr 1997 10:35:00 -0700
   Subject: P21 Boot Help
   From: Dave Lowry <lowry@htc.honeywell.com>

   I've been going through the ROM from Ting's '21H kit, trying to understand
   how P21 boots.
   ...

Lack of comments in the code, but not too hard to reconstitute.

The only non-volatile memory in P21 is 8bits ROM, there is no disk to load
programs from during boot.  So P21 boots from slow 8bits ROM, in the very
slow and limited 8bits instructions mode, which is just enough to download
application code in 20bits RAM (usually DRAM), building every 20bits DRAM
word from 3 consecutive ROM bytes.

The only code that the 8bits mode downloads is usually a 20bits mode downloader
(only 16 words of code, almost identical to the 8bits mode version) to which it
jumps, thus switching to fast 20bits mode (4 instructions per word fetched).

The DRAM downloader is made of a first "byte" subroutine which shifts its "T"
argument 7bits left (after a first shift left executed before calling byte),
pushes an 0xFF mask, fetches the next byte from ROM at the address contained in
A (post-incremented), ANDs it with the mask to clear the top 13 bits (which are
equal to the 13 top bits of the byte address) and finally XORs it with its "T"
argument ; for C speakers : T = (T << 7) ^ (0xFF & *A++);
   ( byte ) 
   2* 2* 2* 2*
   2* 2* 2* #
   ( ff )
   @+ and xor ;

The downloader is made of a second "word'" subroutine which first saves on the
return stack the DRAM word destination address contained in A, then sets A to
the ROM byte source address found in T, fetches the 1st byte and shifts it once
before calling "byte" (which fetches and concatenates the 2nd byte), shifts the
result once again before calling "byte" (which fetches and concatenate the 3rd
byte), then exchanges the ROM address of the next byte contained in A with the
DRAM word destination address on the return stack, stores the word built from
the 3 bytes at its destination address (post-incremented), and finally restores
the DRAM destination address in T (A contains the ROM byte source address) ;
for C speakers, "word'" is equivalent to :
  *DRAM++ = ( ( (0xFF&*ROM++) << 8) ^ (0xFF&*ROM++) ) << 8) ^ (0xFF&*ROM++);
   ( word' )
   a push nop a!
   @+ 2* nop nop
   call byte
   2* call byte
   a pop nop a!
   push !+ pop ;

The downloader is made of a main loop "boot" starting (jumped to from the 8bits
mode boot downloader) with A containing the next DRAM location to write to
(which is the famous "+ -until" labelled "MISSING:"), pushes on the data stack
the ROM address from which bytes will be read to build words to write in DRAM
(ROM address built by complementing the complemented literal a8030 to obtain
1a8030), pushes also an initial value to count the words to download, then
enters the loop where the count is saved on the return stack before calling
"word'" and restored after (note that the first 20bits word that the "word'"
subroutine downloads is the famous "+ -until" labelled "MISSING:"), and the
count is incremented by steps of 80 until the carry bit is set (which makes
(100000-800)/80 = 1FF0 steps), after which the application code (following the
"+ -until") is executed.
   ( boot )
   # com # nop
   ( a8030 -# )
   ( 800 )
   ( begin ) push call word'
   pop # nop nop
   ( 80 )
   ( MISSING: + -until )
   ( application code from here )

I hope this explanation will help.
CL