Re: F21c

[wmor1@xxxxxxxxxxxxxxxxxxxxx]

> Date:          Sat, 7 Jun 1997 12:39:15 -0700 (PDT)
> From:          jfox@dnai.com (Jeff Fox)
> To:            MISC
> Subject:       F21c

> Dear MISC readers:
> 

> Power:
> F21b had 3 power and 3 ground, F21c has 6 power and 6 ground. Hopefully
> it is more than we need. If it then some pins may be freed up on F21d.
> Video:
> On F21b Vi Video in was not connected.  On F21c there is no Vi pin.
> The Vo Video out (composite) is also missing on F21c.  F21c has
> only RGB from the video coprocessor.  You will need an RGB monitor
> with the built in video output.

I have a suggestion if enough pins are not freed up for the next 
version of the chip, could the video functions be multi-plexed with 
the RGB port or parrallel port until a version is made with enough 
pins.  We could probably get by with either RGB or video for now, if 
we could choose.  Extra serial pins multiplexed on the parrellel port 
would help with more complex network structures.

> Peter Jakacki wrote:
> >I am offering a suggestion for the on-chip ROM on the F21 to allow
> >booting a system without an external EPROM.
> 
> The original F21 spec allowed F21 to boot from the network.  This
> means that no matter how many F21 you have you only need one to
> boot of ROM (FLASH/NVSRAM/EPROM).  We may get that feature back
> before production.  If not it adds a ROM to each node in the design.
> 
> >32K byte serial EEPROMs are available that require only 2 I/O lines
> >clk+data) to be accessed. 
> >
> >Could the boot ROM include routines to read user code from here into
> >RAM for execution. Also, some method would be needed to download via
> >a serial port directly into RAM or the serial EEPROM.
> >
> >Actually, this is not really a question, more of a plea.
> >
> >I'd be more than happy to implement the code necessary once I get some
> >idea of the size of the on-chip ROM available. I guess that the code
> >would only require a few hundred bytes, although 1K would be more
> >reasonable to allow for improved serial drivers etc.

I think it is a good idea as the processor has to load in it's code 
from 8-bit rom to dram anyway to perform it in dram (this is apart from any 
initial boot code).  Nationals' feild bus(?) is supposed to be new big 
standard and the price of their 4Mbit flash memory is cheap (and only 
requires serial programming without the need for extra specialised
programming hardware), apart from that we have the slower Microchip
devices etc.  If we could add USB hardware support we would have a 
large base for periphials.   Talking about pleas what about Firewire buss 
or USB for the x32.
> 
> It also sounds like a waste of the highest speed part of the chip to
> do the slowest thing that it would do.
> 
Yes you are right, booting and high speed functions (math functions 
please if possible) that need it would be good.

Thanks Jeff and congradulations.

Wayne. 

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Wayne Morellini  <wmor1@student.monash.edu.au>

Post Graduate Student Representative.
Rusden Campus, Deakin University, Vic, Australia.

GradDip Media Studies (Current), Bach InfoTech & AD Business(Computing).
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