Re: Speculation on ARM licensed by DRAM companies

[Eugene Leitl <Eugene.Leitl@xxxxxxxxxxxxxxxxxxx>]

On Sun, 20 Jul 1997, WMOR1 wrote:

> I ran accross this today in the Arm microprocessor group, thought it 
> maybe of interest.

It _is_ of interest. I've just revived by Novix 4000 board, and got some 
ARM Forth listings as I contemplate porting them to my Newton 130. It 
appears ARM has a good architecture to do Forth with.
 
> Wayne.
> 
> torbenm@diku.dk (Torben AEgidius Mogensen) wrote:
> >With Hyundai as the newest licensee of ARM, there are now a number of
> >the largest DRAM manufacturers that have licensed ARM cores. This
> >leads me to speculate on whether we in the future will see DRAM with
> >integrated ARM cores. About a year ago I read a paper (I think it was
> >in Computer Architecture News and entitled "Breaking the Memory Wall"
> >or something similar) that speculated that it may be a good idea to
> >put a simple RISC core on a DRAM chip. The arguments were:

Anybody noticed the avent of DSPs with large (1-4 MBit) on-die SRAMs?
I am referring particularly to ADSP-21061 & family, and TI's C6x chip.
Notice that the latter features a 256 bit broad on-die bus and VLIW, a 
point I have been talking about for years.

> >DRAM technology is typically as dense (or moreso) than typical CPU
> >technology, the difference being mainly that fewer layers are

DRAM can do more: >1 Gbit densities are available in the lab for years. 
With defect-tolerance (defect marking), such densities should be 
achievable in the industrial reality.

> >available. But a suitably simple RISC design can be build to run
> >reasonably fast even with this limitation. The authors (being from
> >Sun) suggested a simplified Sparc core, but ARM seems like an obvious
> >possibility. When the CPU is on the same chip as the DRAM, a lot of
> >the time (and power) required to drive the signals across a bus is
> >avoided, so you can get far lower latencies than with similar DRAM

Yeah, the difference between a DRAM and an SRAM cell may matter 
significantly less if we are talking of on-die accesses and tiny geometries.

> >technology on separate chips. The line buffers in the DRAM can easily
> >be modified to work as cache for the CPU. With 128Mb and 256Mb DRAM
> >coming shortly, this would be enough for small systems, e.g. NCs, PDAs
> >or game consoles. Even with smaller DRAMS, it would be ideal for
> >embedded systems.

This is wrong. The point is to make the dies small enough, so defect hits 
achieve just a tolerable 50% on one wafer. Using redundant wiring on the 
wafer, the resulting WSI computer would still be fully functional (i.e. 
100% wafer yield). This eliminates a lot of additional processes and 
tests, making the product cheaper. Since resulting fine-grained maspar 
systems feature ~1 MBit grains, this may mean a revival for Forth.

It won't happen, of course. Forth has sunk beneath the perception 
threshold of the mainstream. Forth society membership numbers have been 
shrinking in Germany. 

> >This type of applications is exactly what ARM is mostly used for, so
> >it seems like an obvious development. However, it would require a
> >redesign of the ARM core to DRAM technology, something which the
> >present licenses (AFAIK) do not cover. A license similar to the one
> >DEC got to develop StrongARM would fit the bill, though.

The MISC core would be ideal for that, but I guess we just can't clone 
Chuck. How's the set top box is progressing, btw? Java based NCs being 
delayed, this could mean a true chance for it (I keep my fingers crossed).

I am also looking forward to the F21. But notice how much has occured 
interim, especially the advent of Beowulfs, and 1 Gbit ethernet. Mass 
production makes even inefficient monster hardware ridiculously cheap, a 
large handicap for MISC.

ciao,
'gene

> >	Torben Mogensen (torbenm@diku.dk)
> >
> >P.S.
> >Of the 10 posting that were in this group when I read it today, 9 were
> >spams or replies to spam. Maybe it is time to make the group moderated.
> 
> 
> 
> 

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