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UTSi® Technology Overview
Compared to standard CMOS technologies, Peregrine
Semiconductor Corp.'s patented, proprietary UTSi (Ultra-Thin-Silicon) CMOS
process offers advantages in speed, circuit density, and power
consumption. However, its most significant advantage is its
superior ability to combine microwave, analog, and digital functions
onto a single chip.
The UTSi process is a silicon-on-insulator (SOI) technology. With SOI
technologies, circuits are fabricated in a very thin layer of silicon on an
insulating substrate, or in a thin silicon layer that is electrically
insulated from a solid silicon substrate.
Today's complex integrated circuits are fabricated almost exclusively
in CMOS on standard silicon substrates. The availability of
inexpensive, high-quality silicon wafers and an enormous pool of
manufacturing experience, favor standard CMOS for most applications.
However, the migration toward smaller transistor dimensions, the need
to decrease power dissipation, and a desire to combine sensitive
analog circuits with complex digital circuits - particularly in
communications applications - is spurring interest in
alternatives to standard silicon technology.
Conventional CMOS processes build circuits on silicon wafers
about 500 microns thick, but all the circuitry is actually formed in
a 1 micron layer at the surface. These standard silicon devices are
far from ideal - the circuits interact with the conductive
silicon substrate, causing many parasitic effects. In particular,
capacitance between the circuitry and the substrate causes power
consumption to increase with switching speed and creates undesirable
coupling between circuits. The bulk substrate's dispersion of
high-frequency signals precludes the construction of microwave
devices. These effects become more pronounced as advances in
manufacturing technology lead to smaller transistor dimensions and
lower operating voltages. This has caused some technologists to
assert that integrating all the functions necessary for future
wireless communications devices onto a single chip will require a new
technology.
Gallium arsenide (GaAs), the most mature alternative material
technology, may be more suitable than standard silicon CMOS for some
high-frequency devices, but it is not useful for very large digital
circuits. In spite of its long history, GaAs still faces numerous
manufacturing and device-physics challenges. More recently developed
materials (silicon-germanium, silicon carbide) are probably many
years away from being commercially viable. The most desirable
solution to future design problems would be to continue using
silicon. Silicon is unique- it is the only element with
numerous physical properties that make it inherently suited to use in
integrated circuits. The industry has an enormous investment in the
design and manufacturing of silicon circuits. For some time to come,
silicon will be the first choice, perhaps the only choice, for
fabrication of complex ICs. It will be necessary, then, to eliminate
as many undesirable bulk-silicon parasitic effects as possible.
If transistors could be fabricated in a very thin layer of
silicon on an electrically insulating substrate, nearly ideal devices
could be realized. This is the reason for the recent surge of
interest in SOI technologies. Submicron transistors require very
high-quality silicon, but there are substantial difficulties in
obtaining a defect-free silicon film on an insulating substrate. The
most mature SOI process is silicon-on-sapphire (SOS), in which a thin
film of silicon is grown on a sapphire wafer. SOS is an established
technology used primarily in military and space applications, where
its inherent resistance to the effects of radiation is essential.
While SOS has been proven manufacturable and has significant
performance advantages, it has seen little commercial use, mainly because
SOS has been unsuitable to the fabrication of the very small
transistors needed for modern, high-density circuits.
When silicon is grown on a sapphire substrate, differences in the
crystal lattice dimensions of the sapphire and silicon cause the
silicon to form with many microscopic dislocations. These
dislocations, which are more numerous near the silicon-sapphire
interface, interfere with the movement of electrons through the
silicon. The concentration of defects near the interface effectively
prevents the use of the very thin silicon films necessary for
deep-submicron transistors.
One cumbersome alternative to using a sapphire substrate is to produce a thin
silicon layer on top of a silicon-dioxide layer on a bulk silicon
substrate. Two of the more successful methods used for this type of
SOI are wafer bonding and SIMOX (Separation by IMplanted OXygen).
Since single-crystal silicon cannot be grown on amorphous silicon
dioxide, both methods seek to insert an insulating oxide layer
between existing layers of silicon. Both processes are complicated,
time consuming, and costly.
In the wafer bonding process, two oxidized bulk wafers are bonded
together. Polishing or etching the top wafer leaves a thin layer of
silicon supported by the bottom wafer but insulated from it by an
oxide layer. This is mechanically a difficult process, requiring
extremely clean wafer surfaces to prevent voids. Doping procedures
used to control the etching of the thick upper wafer increase the
defect density in the final silicon layer. This technique is most
appropriate in applications that require thicker silicon and silicon
dioxide layers.
In a very different procedure, the SIMOX process implants oxygen
atoms just beneath the wafer's surface, creating a thin, buried layer
of silicon dioxide. High implant energies and multiple
implant-and-anneal cycles are required, since the implantation
process severely damages the silicon overlayer.
SIMOX and other Si/SiO2/Si technologies may enable the
fabrication of smaller transistors by providing a thin layer of
silicon, but there are compromises in performance. Because silicon
dioxide is a poor thermal conductor, that layer must be kept very
thin. Still, self-heating effects degrade transistor performance in
SIMOX devices. Also, the circuitry, although electrically insulated
from the conductive silicon below, is close to it and remains subject
to many of the parasitic effects seen in conventional bulk-silicon
circuits. High-frequency dispersion losses, for example, persist.
The ideal solution would be an extremely thin, high-quality silicon
film on a thick, electrically nonconductive (but thermally
conductive) substrate. This is what UTSi technology offers.
Peregrine's UTSi process begins with a conventional SOS wafer. The
silicon film is improved through a series of ion-implantation and
annealing steps, then thinned by oxidizing and etching. The result is
an ultra-thin (0.1- micron) film with a low defect density. UTSi
wafers can be processed on existing CMOS fabrication lines with
minimal changes to the standard process and fewer yield-limiting
steps. Circuit design is easier as well, since the UTSi process is
essentially standard CMOS without many of the parasitic effects
inherent in bulk silicon processes. Higher packing densities and
improved yields offset the cost of the sapphire substrate, making
UTSi components cost-competitive.
Peregrine has demonstrated a field-programmable gate array, a 64-kb
SRAM, a 2.5-GHz frequency synthesizer, and various microwave devices
in its UTSi CMOS technology. The microwave devices were fabricated on
the same die as the SRAM, demonstrating the ability of the UTSi
process to combine sensitive analog devices and large, high-speed
digital devices in a single process. UTSi circuits exhibit many
characteristics of an ideal SOI process: higher speed, lower power
consumption, inherent isolation between circuits, and improved
yield.
Of the various SOI technologies being investigated by commercial IC
manufacturers, UTSi technology is the most promising for implementing
highly integrated, multiple-function, low-power ICs. Such ICs will be
needed for the wireless communications market to develop to its full
potential. Peregrine Semiconductor Corp. is currently the only
company dedicated to the development of commercial IC products in
this technology.
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Peregrine, Peregrine Semiconductor Corp., UTSi, and logo are all registered trademarks of Peregrine Semiconductor Corp.
Peregrine Semiconductor Corp., 6175 Nancy Ridge Drive, San Diego, CA 92121, (619) 455-0660, Fax (619) 455-0770
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