Re: MISC-d Digest V98 #28

[Penio Penev <penev@xxxxxxx>]

On Fri, 17 Jul 1998, GARY B. LAWRENCE wrote:

|      I would like to get some feedback from this group on a subject that
| interests me at the moment. I would like to see F21's be used in a 
| multiprocessor version of a multitasking operating system. 

To do that "transparently" is not trivial -- there is the "memory
coherence" issue.  SGI is moving heavily into this direction with their
ccNUMA (cache-coherent Non-Uniform-Memory-Architecture), quite
successfully, I might add.

This is interesting in its own right, since the same interfaces that were
in use in 1990 continue to be in use now, with much more power (Blue
Mountain, they call it nowadays :-)  Briefly, one starts (sproc) as many
IRIX processes as there are processors, so the OS has a chance to schedule
all of them at the same time.  Then, one uses the native OS spin-lock
mechanism to serialize the (polyFORTH-like) WAKE operation, which wakes a
FORTH task.  Using the same spin-locks, one implements the
(polyFORTH-like) semaphore GRAB .  Voila, you have a FORTH running on the
fastest supercomputer on Earth.  You can have as many FORTH tasks as you
want, and all available processor will chase the tasks that are ready to
a-WAKE-n.

This scenario is very unlikely for a MISC design.  It is contrary to the
goal of "low fat computing" (term courtesy of Chuck and Jeff).

My feeling is that one needs to make "appliances" -- special-purpose
devices, which are way ahead of "general purpose" device in
price/performance (anybody heard lately of Larry Ellison :-)

MISC is a very suitable vehicle for appliances.  It remains to be seen
when enough critical mass will amass :-)


--
Penio Penev <Penev@pisa.Rockefeller.edu> 1-212-327-7423