Re: clockless logic

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

The AMULET Group Home Page at http://www.cs.man.ac.uk/amulet/
is a good starting point for informations about asynchronous logic.

Asynchronous logic is not properly speaking "clockless", although it has no
centralized/broadcasted clock, but a lot of independent/distributed "clocks"
(which may be aperiodic) providing local synchronization between registers.
The goal of asynchronous logic design is to be as independent as possible of
gates and wires delays, local synchronizations letting the chip work as fast as
possible whatever its temperature or supply voltage.  A fully asychronous adder
takes different times to execute depending on the temperature, the supply
voltage, and the length of the carry ripple, itself depending on the added
data.  However, if the suppression of the centralized/broadcasted clock net
saves a lot of chip area, power dissipation, and clock skew problems, the added
gates and wires required for synchronization make it hard to decide a priori
whether an asynchronous design will, compared with an equivalent synchronous
design, be faster (or slower), smaller (or bigger), or dissipate less (or more)
power.  The main interest in asynchronous design is its ability to assemble
modules by simply connecting smaller modules, without stressing for clock
distribution and skew, or even for gates and wire delays (except for
effficiency).

Chuck's x21 chips are also not properly speaking "clockless".  Although they
have no external periodic input clock, they internally generate a centralized
"clock" with an oscillator which period may be changed at each cycle (think of
a pendulum which length may be changed at each oscillation), depending on the
processor state (mainly the current instruction code, the instruction slot
pointer, the address registers A,R,P, and previous DRAM page address register).
This "clock" drives, through various decoding/delaying circuits, each register
strobe which samples the register input to change the register state/output.
Chuck's x21 chips are clearly not designed independently of gates and wires
delays (no synchronizing gates, except between co/processors). In the contrary,
gates and wires delays are taken into account at a fine granularity level to
check (with the OKAD silicon simulator) that signals at the input of a register
will stabilize before the occurence of the register strobe pulse (no expensive
global minimal-skew clock net).

Together with the stack-architecture and its 0-operand minimal instruction set,
this self-timed "delay-tuned" design makes the x21 family very efficient ...
but also very sensitive to inaccuracies in the model of the silicon process,
used to predict the gates and wires delays, as have shown the last 6 years of
Chuck's efforts.

CL
--
http://www-rocq.inria.fr/who/Christophe.Lavarenne