Fw: f21 pcb or computer at UT

["Myron Plichota" <mplichot@xxxxxxxxx>]

I have not received a reply or non-delivery report to this. I repeat this
offer in all sincerity in public. I would hate to see the F21 die,
especially so close to fruition. Did I say something wrong?

BTW my estimate is 1 week layout, 2 weeks fab = 3 wks turnaround once the
missing info is supplied.

-----Original Message-----
From: Myron Plichota <mplichot@sonic.net>
To: Jeff Fox <jfox@UltraTechnology.com>
Date: Wednesday, March 10, 1999 12:46 AM
Subject: Re: f21 pcb or computer at UT


>Dear Jeff,
>
>I volunteer a *donation* of the following (go ahead and buy the new
>computer):
>
>1) A clean schematic in Protel
>2) A 4-layer layout in Protel that is guaranteed to match the schematic
>netlist
>3) A panel of finished boards, quantity TBD
>4) A copy of all the design files
>
>I feel that a 4-layer board is worth the extra cost because of better power
>supply decoupling, signal integrity, and a layout that caters to the
>signals, rather than the power supply. Also, I once had an otherwise sound
>design flake out because an asshole manager couldn't resist
>nickle-and-diming the PCB down to 2 layers. Boy, did I rub his nose in it
>when it was simply relayed-out with 4 layers with no other changes and
>worked perfectly. Despite the really fast stuff confined to on-chip, my
>instinct is to go 4 layers. I would rather pay the extra money in order to
>donate the best possible chance for successful testing.
>
>I have studied the pdf F21 data sheet and there is just not enough info to
>procede without further details. The ASCII pinouts have at least 1 error
>(the CLCC outline should have 17 pins on each side) and the hints for
>interconnection are delphic. You gotta give me something to work with. In
>return for some unhasty, proofread documentation I can guaranty you a whack
>o' boards that meet your goals.
>
>I understand or recommend the following:
>1) 10uF tantalum (plus 0.1uF ceramic) decoupling for F21
>2) 100K to V+, 0.1uF to V- for reset circuit
>3) 0.100" dual-row test headers around F21 for signal access
>4) inductor or resistor series feed for analog V+, plus tantalum plus
>ceramic decoupling
>5) a coprocessor xtal oscillator site
>6) specialized outside world connectors
>7) a 0.100" grid wirewrap area
>8) an adjustable linear voltage regulator w/AC adapter plug
>9) low-inductance SMT footprints for the decoupling caps
>10) #6 mtg. holes in corners
>
>I request more info on the following:
>1) a pin-by-pin signal discription of the F21 (pin number, pin name,
>purpose, restrictions)
>2) the mfgr and *complete* part number for the DRAM and boot ROM you intend
>to use. I will verify footprints to the mfgr's data sheets. If you cannot
>provide this, then some discretionary guidelines will do.
>3) any particular connector requirements
>4) presence/absence of video series resistors
>5) anything else you can think of or corrections to any assumptions I have
>made
>6) a short list of links to existing *definitive* documentation that I may
>be unaware of, have forgotten, or missed the significance of
>
>I would be proud to make this contribution to the quest for lean computing.
>I believe a simple PCB could be turned around in 2 weeks (1 wk design, 1 wk
>fab) upon your approval of the schematic and partslist. I could zip the
>schematic printed to file or make arrangements to deliver hardcopy.
>
>I was dismayed to find that you were having such a rough time and on the
>verge of packing it in. Believe me, I would have offered my support sooner,
>but I was under the impression that these efforts were operating with
>funding, however marginal, and staffed by a closed elite.
>
>As an embedded systems designer, I regard clear documentation as a
>prerequisite to even consider a design win. I have a suggestion or two for
>your serene contemplation regarding how to respond to redundant questions
>from your audience: simply beef up your pdf datasheet and post the
>availabilty of each new edition. Put a link to it right at the top of your
>webpage instead of tucking it away in the simulator zip file. Do not
scatter
>F21 engineering info around in tiny fragments, give your audience
>1-stop-shopping.
>
>I am a guy who has had Zen values long before I ever used Forth (1980) and
>lack neither intelligence nor patience, but most of the MISC articles only
>give me a historical perspective. I might muddle through it all but my time
>is spent juggling too many other balls. This is not to say that the
articles
>do not cause my admiration and inspire me to rethink Forth h/w and s/w, but
>I could not sell a 21-bit Forth chip to my boss based on what I have seen
so
>far, and I wish it was not so. The industry standards are high, at least
>with respect to hardware documentation.
>
>Best regards,
>
>Myron Plichota
>Healdsburg CA
>
>