Re: Funding

[msimon@xxxxxxxxxx (M. Simon)]

Sorry about resending this. I got the addresses screwed.

Simon

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>Is it already what the DYOP offer gives you: a FORTH processor in FPGA?

Yep.

An aside here.

    Xilinx has forced a speed upgrade on me. I can no longer get the 
-3 parts. They only have -2 parts now. As time goes on I expect this 
trend to continue.

At the top speed grades a 32 bit adder takes about 11 nS a 16 bit takes
a little over 8 nS. Cycle times on the order of 20 nS ought to be possible.
From a CPU costing about $50 to $75 with all auxilary peripheratls included
(I/O ports, counters, 4 to 6 bit DACs etc) and the exact peripherals your 
application requires. About 1/10th the speed of Jeffs stuff. But you
get the I/O you want. And you can optimise the processor for the application.
Something hard to do with hard silicon unless you are moving a lot of
wafers.
Simon - http://www.tefbbs.com/spacetime/index.htm