Re: DYOPFunding

[msimon@xxxxxxxxxx (M. Simon)]

Only Xilinx. The way the PLDs are loaded is different for each mfg.
As are the synthesis tools.

It would cost about $2K to extend the design to another PLD mfg.

Simon
================================================================
>Hello Simon,
>
>Can this FORTH processor be designed using the PLDs from Lattice or only
>the Xilinx varieties are appropriate?
>
>Thanks & Regards...Das
> 
>At 02:24 AM 3/17/99 -0400, you wrote:
>>
>>Sorry about resending this. I got the addresses screwed.
>>
>>Simon
>>
>>============================
>>
>>>Is it already what the DYOP offer gives you: a FORTH processor in FPGA?
>>
>>Yep.
>>
>>An aside here.
>>
>>    Xilinx has forced a speed upgrade on me. I can no longer get the 
>>-3 parts. They only have -2 parts now. As time goes on I expect this 
>>trend to continue.
>>
>>At the top speed grades a 32 bit adder takes about 11 nS a 16 bit takes
>>a little over 8 nS. Cycle times on the order of 20 nS ought to be possible.
>>From a CPU costing about $50 to $75 with all auxilary peripheratls included
>>(I/O ports, counters, 4 to 6 bit DACs etc) and the exact peripherals your 
>>application requires. About 1/10th the speed of Jeffs stuff. But you
>>get the I/O you want. And you can optimise the processor for the application.
>>Something hard to do with hard silicon unless you are moving a lot of
>>wafers.
>>Simon - http://www.tefbbs.com/spacetime/index.htm
>>
>>
>>
>>
>
Simon - http://www.tefbbs.com/spacetime/index.htm