Re: Support for UT
- To: MISC
- Subject: Re: Support for UT
- From: msimon@xxxxxxxxxx (M. Simon)
- Date: Fri, 19 Mar 1999 06:53:03 -0400 (EST)
>>> Looks like if we want some FORTH processors, DYOP is better,
>>> but then, it won't bring either performance or price.
I don't think I responded adequately to this point.
Because DYOP is FPGA you can often add special hardware to speed problem
solutions. This can sometimes make up for much of the 10x - 20x speed
difference between hard silicon and programable silicon.
Plus with FPGAs pins are relatively cheap. 3 5bit (RGB) DACs are no
problem nor is a separate video controller with its own RAM (no processor
slowdown - dual ported for processor access) to pump out pixels.
Or a serial data pump. Or ?
Not as elegant as Jeff/Chucks stuff but the risk is much less.
Simon - http://www.tefbbs.com/spacetime/index.htm