RE: support, T-shirts, etc. (composite reply)
- To: MISC
- Subject: RE: support, T-shirts, etc. (composite reply)
- From: msimon@xxxxxxxxxx (M. Simon)
- Date: Sun, 21 Mar 1999 02:12:45 -0400 (EST)
I was goint to risk my own $$$ on the board. It would have been used
to bring up the F21 and if it was working good enough we would have
a product.
I use this method all the time to shorten development to payoff time.
If it didn't work - I lost my $$$ and Jeff gained some help.
I'm focusing on FPGAs, speeds are going up, prices down, risks minimal.
And I can do 2 - 6 FABs a day for only the cost of my time. Jeff can do
one FAB every three months if he has the $10K.
Jeff has the ultimate in speed and effiency. I can often add
custom instructions and hardware in the FPGA to make up a
lot of the difference.
Would I like an F21? You bet.
But I want to suceed in the market place. To do this I have to lower
the risk. Proprietary chips from companies with no track record
run by 'flakes' do not inspire confidence.
We have a very good technology model run by some very competent
people. Thanks to Chuck, Jeff, and many others.
What we are missing is a working business model.
My claim is that as insurgents the Grateful Dead model is
more useful than the IBM model.
I have been preparing my plan for 3 years. I am in the process
of execution. We shall see.
We need more FORTH application articles in mainstream magazines.
Control systems and the like. Where FORTH is incidental to the
application.
I'm working on teaching machine tool users FORTH.
Inside and outside the box.
Programmers are not our only market.
Simon
====================================================================
>
>I traded a couple of emails with Jeff about the PC board just before he
>went on vacation. He says the
>timing of the product oriented boards was premature.
>I have offered to help with test orinted boards, but
>he already went off the list and on vacation, so I have not heard back. I'm
>proceeding with some preliminary work with what I know. I know he needs
>boards with lots of test points, and yet, for his
>temperament, they need to be small and simple and
>easily revised too. So, I'm working on a simple layout
>with 1.5mm X 3mm surface mount test clip loops attached.
>
>> -----Original Message-----
>> From: M. Simon [mailto:msimon@tefbbs.com]
>> Sent: Wednesday, March 17, 1999 11:24 PM
>What I wanted to do was design a F21 board suitable to run the tool.
>I need something as fast as F21 to do 3 axis contour milling.
>
>The board I wanted to do for Jeff would be suitable.
>
>Since Jeff is not interested I plan do do what I need in FPGA with perhaps
>a custom processor segment to speed some of the operations.
>
>
Simon - http://www.tefbbs.com/spacetime/index.htm