P16 In FPGA Update
- To: MISC
- Subject: P16 In FPGA Update
- From: Dave Lowry <lowry@xxxxxxxxxxxxxxxxx>
- Date: Sun, 21 Mar 1999 09:10:19 -0600 (CST)
P16 is now running from external EPROM. The speed is limited to
about 10 MHz due to the EPROM's 100 nsec access time.
A portion of the video coprocessor is done. It displays IBM-PC
monochrome video. The final horizontal resolution will be
determined by the CPU clock, but will probably be 640 dots.
Vertical is 350 lines.
The arbitration between the video and CPU is *not* done yet,
so all I can display is a fixed pattern. The video will
be synchronised with the CPU to avoid the "sparklies" that
plagued MuP21.
This is a hardware video display... not the extremely clever
instruction-based video devised for MuP21. Oh well.
Without video, and with 5 deep data and return stacks, P16 fits
in a little more than 1/2 of a Xilinx 4010. With some
smarter coding, it *might* just fit in a 4005, but I want
bigger stacks than MuP21 had.
Higher res or color video is not an option, due to the limited
16 bit address space.
More in a few days.
-Dave
