Chuck Moore's talk to SVFig on 5/22/99 part 1

[theFox@xxxxxxxxxxxxxxxxxxx (Jeff Fox)]

Dear Misc mail list readers:

I have started an html page http://www.ultratechnology.com/cm52299.htm

with the transcript of Chuck's last presentation.  So far I have only
done part 1 of 6.

(part 1) <B>Charles Moore</B><BR>
I asked a question on comp.lang.forth to see what I should talk about today and
I got a, (pause) I got a reaction. (laughter)
I will talk about maybe 10% of it. It had to agree with
what I was going to already say you see.  But I invite you to do the same. I
will stop early enough that less than trivial questions can be asked.<P>

To answer one question: iTV is alive and well. Things look very promising
who will say what will happen next week. But we are working at it.
I am not permitted to say more than that except that, an amuse aside,
we had a due diligence review from a silicon valley technical expert.
I was looking forward to this because I wanted to see what a real authority
would say about what we were doing. It was disastrous, absolutely disastrous.
I think the kindest word he said was esthetically elegant and the
harshest word was anachronistic. And in a sense he is accurate.
Silicon valley is not looking forward to the products that we are making.<P>

Q: Who is this person?<BR>
Chuck: I shouldn't say.  He is a respected authority.  I would welcome a
chance to debate him some time. But that will never happen.<P>

(graphic to be inserted here)<PRE>
1000  .
500   . . .
    0 . . . . 1.0</PRE>

Here is an interesting picture.  We are talking to a new fab.  We burned
through two fabs.  I don't know if you know this but. But
the HP .8 micron is gone and that is what
I was using for the last four years.  We ported to
a .6 micron process at LG last year but that is now gone.<P>

This fab had a lot of different processes so I had a chance to make this
picture on the right you see the feature size from .1 to 1 micron.
and vertically is the number of
micro amps of current per micro meter of transistor width.
So this is the current through a transistor.
Roughly speaking the speed of a process is going to be proportional to the
current through the transistor.  That is about the only variable left.
Here we are at .8 micron at about 500 and that just happens to be mips
too, which is convenient.
If we were at one we would be slower if we were at .5 or .6 we would
be faster but not by much.
This is five volts (in black), this is three volts in red.  And when
you go to three volts you slow way down because you aren't going to
get as much current.  This is .35 and this is .25.<P>

I've plotted it offscale too to make it look linear.
It is interesting that is mostly linear on each line (5V and 3V).
This is an IBM process up here at .2 (u) and 1.5V and that to me
is enormously impressive. Given that these are the marginal gains
that you get at 3V to get way up there at 1.5.  I would like to work
with that process. But that is only a factor of 2 in speed
from where we are now.  Which is a little bit disappointing.
I think it may be more than that, maybe 2.5 or 3. You can't
know until you try. But these are going to be 50% faster
than we are now but not a factor of two. (pointing to .25 and .35)
And at a fairly considerable cost in going to smaller geometries
in cost, dollars.
The smaller geometries cost you more than larger ones.
That is why we were sitting at .8 for so long
because it was a nice mature comfortable process
low cost fabrication.  we can't sit there, this is obsolete
there is no particular reason to move to there
unless we run out of speed.<P>

One of the criticisms of our process is that we were claiming these
ridiculous speeds.  But everybody in the world has agreed that Drystone
mips as the proper measure of processor speed... Now
am I wrong is saying that Drystone mips measures 'C' compiler performance?
That has nothing to do with processors. That is a weird comment to make.<P>

These speeds are, I think, honest.
I have been claiming, I have been telling you for years, that
this is burst rate (pointing to 500 mips)
for a series of four instructions and
then we have to wait for memory access.<P>

Well I spent some time building and designing an
SDRAM interface.  SDRAM will give me 10ns access to a significant amount
of memory. Something that was long overdue.
I've got to redesign the memory interface and the interface to the
coprocessors to take advantage of that. And when I do,
and that is another months work, if it is funded,
I'll have a sustained 500 mips.<P>

If we were to go to .35 I would have
a burst of 600 mips but I can't sustain it.  I certainly can't
sustain 1000 mips because memory isn't fast enough any more.
If I get 4 instructions per word, you take whatever your memory access
rate is and you divide that by four and that is the maximum speed that
can be sustained. I have always felt comfortable having a clock speed
two or three times as fast as I needed so I would have something to
do with it. SDRAM may do that.<P>

(part 2)<BR>
all right let's go on to what people really want to hear about.  This
was one of the most popular questions.<P>

ANS Forth is an increasingly significant fact of life in the world
as we know it. It may not to be to my taste but I think it is to lots
of people's and I have no quarrel with it.
What is it that I don't like about ANS Forth?<P>

This page is in the process of being transcribed, please be patient.
parts 2-6 will follow.<P>