Re: lean + mean

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

> Out of curiousity: is the SHARC architecture (Analog Devices DSP family)
> suitable for Forth? (Due to it's limited on-die memory one obviously requires
> a very compact OS, and I'd like to build a DSP array as the next step after
> my Beowulf (if only Athlon was already available in quantities!)).

The SHARC ADSP21060 has 4 Mbits of dual-ported on-chip SRAM (i.e. 512 Kbytes,
accessible by 16, 32 or 48 bits words), which is quite a lot, and may access
a lot of external SRAM/DRAM, including the on-chip SRAM of up to five other
SHARCs sharing the same external memory bus.  Multi-megs OS designers may waste
memory at will with the SHARC as they do with other processors.  Compact OS
designers are rewarded by efficiency.  See http://www-rocq.inria.fr/syndex/
for very compact and efficient multi-DSP SYNchronized Distributed EXecutives.

The SHARC is of course suitable for Forth, but not for driving a VGA display,
or an FDDI/SCSI/USB/...  Because integer/FP computation and memory addressing
are done by separate units, using separate register files, "machine Forth" is
(much!) easier to implement efficiently than ans-Forth: most primitives being
one or two assembly instructions, subroutine-threading and primitive-inlining
are very efficient and easy to implement (by "machine Forth" I mean @ @+ ! !+
using an address register and pushing/@ popping/! the stack once, as in F21).

SHARC instructions being 48bits wide, you'd better start with a 32bits Forth
to write a (cross/umbilical) compiler.  Have also a look at the cheap 16bits
ADSP218x, which has a lot of on-chip features, ideal for embedded (multi)DSP
applications.  I've written an umbilical assembler for it, and I enjoy it.

Thanks for gforth :-)
CL
--
http://www-rocq.inria.fr/~lavarenn/