Re: MISC-d Digest V99 #105

["Wayne Morellini" <waynemm@xxxxxxxxxxx>]

Hello sz

I'll answer some of the questions because you have been so helpful before, 
and not so many people are using the list now a days.

From: sz <sz@uc.ru>To: "MISC@pisa. rockefeller. edu" <MISC>Subject: F21 and 
possible enhacements.Date: Thu, 23 Dec

Hello Misc@pisa.,

  I've discussed some of F21 features in our Russian FIDOnet
  conference and my opponent points me that F21 works at 100MHz
  because it can't get faster in 0.35 technology. As far as I remember
  it's untrue. Am I right?

You are right the 100Mhz was either for the p21 1.2 or .8 micron, or the 
speed running from dram  (due to pad power up time limitations in the memory 
interface).  I do wish they (Chuck's misc cpu's) would move to DDR-ram, 
SDRAM or SRAM, but that is probably financially out of reach now.   What is 
the transistor count for pure  F21 command execution core?  Good question, 
everything was supoosed to be less than 15,000 tranistores, maybe less than 
9000, based on the old p21.


  Also, what is real state of stack computers?

? Usefull for tasks that don't require existing register CPU, and leading 
edge.


  Why mainstream goes
  register CPU? Because stacks are slower to access, or because
  mainstream did not develop suitable technology to handle stacks?

Why go Microsoft, PC, BMX bikes, BMW/Citroen CV2, western Qwerty Keyboard 
etc = fashion, right place, right time etc and being stuck with it.

Best regards,
sz                          mailto:sz@uc.ru

Merry Christmas and a happy new Mellenium (or Y2KB experience for those in 
system admin;) to you sz and all Miscers.

Wayne

P.S. sz calculate that only 1-2 cycles are needed to render each pixel in 
voxels, with *8 that much for photo realism.  I suggest that you stick with 
voxels, maybe usefull for a MISC extension, or with programmable silicon a 
hardware accelerator.

Wayne
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