Re[2]: F21 and possible enhancements.

[sz <sz@xxxxx>]

Hello Joe,

вторник, 28 декабря 1999 г., you wrote:

JZ> Serguey,

>>F21 works at 100MHz because it can't get faster in 0.35 technology

JZ> While Jeff should answer this, the F21 has been implemented in 0.8um
JZ> technology. In this technology the typical instruction executes in 2ns (or
JZ> theoretically 500MIPS). Of course practical memory implementations will
JZ> reduce the performance somewhat. Sometimes people propose things like DDR
JZ> SDRAM (e.g., 200MHz devices provide words of memory each 5ns). While these
JZ> devices have a very high data transfer rate in burst mode, they have a high
JZ> start-up overhead and need long bursts 4 - 8 words to achieve a high
JZ> average rate. In order to operate in burst mode you need to use cache based
JZ> memory access. To do this and maintain a high peak memory bandwidth
JZ> requires a somewhat sophisticated cache and extensive instruction profiling.

JZ> With the cost of the DDR SDRAM memories and increased cost of cache and
JZ> cache management I am not sure that the resulting design is consistent with
JZ> the F21 objective of a sub $1 processor.

"Sub $1 processor" - another thing I didn't know about.

>>What is the transistor count for pure
>>  F21 command execution core?
JZ> CPU is about 8,600 transistors.

>>  Also, what is real state of stack computers?
JZ> Except for the small interest a few years ago with the Java hardware, they
JZ> are pretty much dead in the mainstream.

>>Why mainstream goes
>>  register CPU? Because stacks are slower to access, or because
>>  mainstream did not develop suitable technology to handle stacks?

JZ> Mostly because stack machines are less effective for high level languages.
JZ> Advanced compilers can reduce this disadvantage significantly, but stack
JZ> machines are never architecturally better. For hand coded assembly, this is
JZ> not necessarily true.

JZ> In addition, stack machines typically achieve their speed because of their
JZ> simplicity and resource stinginess. Register machines typically achieve
JZ> their speed because of parallism and pipelining. Semiconductor technology
JZ> has been able to increase the number of transistors faster than their speed
JZ> (Order n^2 vs. Order n). Of course there are no laws requiring each design
JZ> not to practice some of the characteristics of the other, e.g., the
JZ> development of RISC register machines taking advantage of advances in
JZ> compiler technology is a perfect example.

I'd like to discuss something slightly aside MISC-list topic - idea of
pervasive multithreaded stack based computer system.

There are three units on complete chip: several F21-alike CPUs, interCPU
communication (message passing) unit and cache unit. Each CPU is very
simple and capable to process several command packed in big word. Each
CPU can send a message with n arguments:
  fork ( x*n n -<label>--)
  Message will be sent to any "idle" (see below) CPU. Message really
  is a request to start execution at label on another CPU and pass on
  entry of label n arguments.

After forking CPU may wait for messages to arrive:
  wait ( -- n*x)

And forked process can become "idle":
  idle ( x*i n --)
  Answering to waiting requestor with n results.

When one CPU encounters difficult task it can split it on several
simpler subtasks and "fork" subtasks to "idle" CPUs. Then it may do it's
job following with "wait" for results to arrive. Then combine them to
get complete result.

That's very alike (as I discovered recently) to Alpha AXP multithread
parallelism. But the key idea is that CPUs are very simple, take small
space on-chip and very fast. We may add task-oriented CPUs - for example,
some that process floating point or SIMD extended - and even have
greater speed for specific frequent tasks.

Key features needed by this approach:
 - fast and small CPU core(s) for easy scalability.
 - fast interCPU communication system (FIFO, or associative memory).
 - cache for memory access.

Languages for this system: Forth or functional languages.

What do you think about it?

JZ> Best wishes,

JZ> Joe


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 sz                            mailto:sz@uc.ru