Re: Simple Forth processor witten in VHDL.

["Myron Plichota" <myron.plichota@xxxxxxxxxxxx>]

Unless you have some trick up your sleeve, you probably want to keep the
fundamental cell size the same as the width of the address bus (eg. 64K
addressing = 16 bits) otherwise there will be obstacles to pointer
arithmetic. A 12-bit design might be worthwhile (remember the PDP-8?) if
you want to conserve target chip resources.

I have recently done a VHDL design for a 16-bit stack machine, but it is
not a dual-stack Forth architecture. The design had to fit within the
limitations of the target CPLD (Cypress Cy37128). In the future, I want to
do a true Forth chip on an FPGA with lots of registers or RAM blocks. If
you are interested, I'll send you the VHDL source.

Whose tool chain are you using in the course? BTW, I have found this VHDL
jazz to be *pretty good* stuff too. The proof of the pudding is to see what
equations are actually generated via the report files. I have yet to see
any equation that could be reduced any further. Hats off to the VHDL
compiler developers, they delivered the goods. I am no seasoned expert in
VHDL, but that didn't prevent design entry and simulation/verification of
my design over a 3 day period of feverish activity. This is extremely
significant technology available to down'n'dirty hobbyists!

Myron Plichota

----------
> From: Don Golding <angelus@ix.netcom.com>
> To: misc@pisa.rockefeller.edu; John Rible <jrible@sandpipers.com>
> Subject: Re: Simple Forth processor witten in VHDL.
> Date: Friday, February 11, 2000 9:10 AM
> 
> Hi everyone.   I am currently half way through a VHDL class now, pretty
good
> stuff.  What I would like to see is a simple 8 bit Forth engine with a
64K
> address space that is writen in VHDL.  This would give you the option of
> creating special purpose co-processors/processes around a Forth core.
> 
> Speed is much less of a concern to me.
> Anyone (or you) working on this?
> 
> Don
> >
>