Re: videoprocessor
- To: Soeren Tiedemann <tiedema@xxxxxxxxxxxxxxxxxxxx>
- Subject: Re: videoprocessor
- From: Tor Silfverberg <d97tsi@xxxxxxxxxx>
- Date: Mon, 03 Apr 2000 17:18:43 +0200
- cc: misc
- In-reply-to: Your message of "Fri, 31 Mar 2000 18:18:00 +0200." <Pine.A41.4.04.10003311740380.22150-100000@sibm7.ruf.uni-freiburg.de>
Aha! ;-)
Many thanks,
/Tor Silfverberg
> Hi Tor!
>
> > Is there anyone out here who knows how the video co-processor on the F21
> > works?
>
> Yes. I have been working on and experimenting with the video coprocessor
> on MuP21 ( that is nearly the same ) and reprogrammed it to match the
> German PAL TV specs.
>
> Does it really execute its own instructions, or is it just reading from
> > postions in memory?
>
> It does execute its own instructions. Every instruction fits into a 5-bit
> slot except for the 'jump' that takes a full. That makes up to 4
> instructions per 20-bit word, pretty much like the main cpu. The
> instructions are:
>
> - P ( Pixel, one of 16 colors )
> - B ( blanking-pulse, identical with black )
>
> - R ( Refresh-pulse for DRAM-memory )
> - S ( Sync-pulse )
> - K ( sKips the next instruction slot )
> - C ( color burst-pulse for composite video )
> - J ( jumps to a destination within 18-bit-page )
>
> - I ( interrupts the main cpu but continuing running. F21 only )
>
> The 'jump' has the format:
>
> 11aaaaaaaaaaaaaaaaaa
>
> Pixels ( and blank ) have the format:
>
> 0igrb : Highest bit of 5-bit group is set to zero, followed by
> intensity bit and the amount of green, red and blue.
>
> The special instructions ( R, S, K, C, I ) have the highest bit set to one
> followed by the 4-bit opcode:
> 1xxxx
>
> The special instruction set keeps the DRAM chips alive and happy ( R ) and
> provide all necessary tools to set up a video frame according to the
> TV-specs. That means horizontal retrace fields ( programmed with ( B, S,
> C and K ) for each scan-line visible on the screen and one or two vertical
> retrace fields, depending upon interlaced image or not. The scan-lines
> continue the Pixel ( color ) information and whole lines are threaded
> together with HR-fields via 'jump' in the appropriate order (interlacing)
> or are just sequential. To maintain exact timing the video coprocessor is
> clocked through an external oszillator. On each tick an instruction is
> executed granting bus time to the cpu between them. The video-coprocessor
> fetches the next instruction word as early as possible. On P21 a
> 14.31818Mhz clock is used because an internal frequency divider produces a
> tick at a rate of 7.159MHz giving a cycle time of 140ns for each
> instruction to execute while a 64us TV-line is built. The 7.159MHz are
> again divided by two to provide the necessary 3.58MHz NTSC-color burst
> that is situated in the back porch of the HR-field and used by the TV to
> sync colors. Without the color burst instructions one gets a black white
> image.
>
> Please refer to Chuck Moores video framing code in OK, to Dr. Tings
> MuP21 Applications Manual or to Jeff's F21 video-specs.
>
> Regards,
>
> Soeren
>