Re: F21/P21 "improvements"
- To: MISC
- Subject: Re: F21/P21 "improvements"
- From: Alan Tutt <alant@xxxxxxxxxxx>
- Date: Mon, 05 Jun 2000 10:05:01 -0400
- Organization: Enchanted Heirlooms
- References: <200006050443.BAA11369@pisa.rockefeller.edu>
Jeff Fox wrote:
"I think enhancements to coprocessors are more in order as the
CPU is already pretty tweaked. The big bottleneck is the
memory interface......"
This may be a question that was covered before I started subscribing to
the list, but what are the design issues with placing memory on the same
chip as the processor? With the designs I see being discussed, it would
appear to me that only about 16KB-64KB of memory is needed, which should
fit onto a normal-sized chip just fine. I know that this would increase
the final production cost of the chip and result in a lower yield, but
wouldn't the performance gains be worth it?
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