RE: F21/P21 "improvements"
- To: misc, Jfox@xxxxxxxxx
- Subject: RE: F21/P21 "improvements"
- From: Lonnie Reed <Lonnie.Reed@xxxxxxxxxxx>
- Date: Mon, 5 Jun 2000 16:51:09 -0700 (PDT)
- Reply-To: Lonnie Reed <Lonnie.Reed@xxxxxxxxxxx>
I am not sure whether this is blue sky stuff, but when I first heard about
it I thought it would mate well with the misc philosophy. One because the
fab process is simple, cheap. And two because it is low/no power, non-volitile,
high speed, high density, compatibility with standard cmos processes. It seems
well suited to on-chip memory.
Basically it is made of a film of the same stuff CD-RW is made of, but it
is electrically read/written to and has higher density than optical read/write.
You can check it out at:
http://www.ovonyx.com/tech_html.html
Lonnie
>>Jeff Fox wrote:
>>
>>"I think enhancements to coprocessors are more in order as the
>>CPU is already pretty tweaked. The big bottleneck is the
>>memory interface......"
>>
>>This may be a question that was covered before I started subscribing to
>>the list, but what are the design issues with placing memory on the same
>>chip as the processor? With the designs I see being discussed, it would
>>appear to me that only about 16KB-64KB of memory is needed, which should
>>fit onto a normal-sized chip just fine. I know that this would increase
>>the final production cost of the chip and result in a lower yield, but
>>wouldn't the performance gains be worth it?
>
>There are a couple of issues. One is the process used. RAM manufactures
>use slightly different techniques than CPU manufactures. That is to say
>compeditive memory chips use tricks like vertical transistors to get very
>dense arrays. Chuck is only using two metal layers and nothing special
>for his chips but he is not using a process normally used for memories.
>
>Cost is an issue. As I have said before we started with the smallest
>packages available to keep costs down. Prototype costs were proportional
>to the number of pins, and they came in various flavors at various times
>depending on the policy of the fab house. One way to look at it was that
>adding a single pin could mean going to a die that costs 2x as much to
>fab. So adding an array of memory would also result in a larger die although
>it could mean a reduction in pins. As I have said before I didn't have
>an extra $40k to add an extra pin (change the memory interface
>substantially)
>
>P8 was an example of a chip with ROM only. I had no pins to outside RAM,
>very small chip. But if you add 128k to 512k bits of memory you are talking
>about making the chip at least 10x bigger possibly much more. I certainly
>didn't have 10x the development funds available.
>
>Chuck has said that on chip memory is generally speaking expensive compared
>to memory chips for the above reasons. Figure out what percentage of most
>big processors are on chip cache and what percentage of the cost it is and
>you see what he means. Chuck has said that he doesn't have the expertise
>to build high density memory arrays on chip and no one has offered to pay
>for him to experiment with that.
>
>It basically comes down to a deal with a company that is making memory chips
>to drop a MISC CPU down on the die with connections to on chip memory. The
>idea is very attractive since you can make chips that are small and need
>few pins. The memory is faster than off-chip memory. The only small
>problem is that it requires a company that is making memory chips that
>wants to do this. It has been very close before but the Asian economy went
>through some rather large bumps a few years ago.
>
>It fits into the long list of things people would do if they had the money
>and resources. Does anyone have an inside track to make such a thing
>happen?
>We get a lot of blue sky stuff from time to time. There are lots of cool
>things
>you could do with million or billion dollar budgets. Anyone have one who
>wants to do such a thing? Bring it up if it is more than just blue sky.
>
>Jeff Fox