RE: F21/P21 "improvements" | memory cost

[Alan Tutt <alant@xxxxxxxxxxx>]

Thanks Jeff for your insights on this issue.

I would like to clarify a couple of things, however.  Before I ask, I'll
begin by saying that I am a part-time hobbyist with very little
background in processor design.  That said, I remember seeing that with
standard-cell technology, blocks of memory can be included in a
processor design.  This was true with the company that (at the time I
ran across the information) was handling the RTX line.  How this
dramatically increases cost I don't know, although for now I will take
your word for it.  I know that you're not working with cell designs, but
with direct designs, which are more efficient.

The viewpoint that I am working on here is not a cache-type memory, as
some readers have seemed to indicate in their responses, but as an
addressable memory block that may be reserved for frequently used code
or data.  In the system that I am envisioning, the on-chip memory would
act like main memory in a desktop system, and off-chip memory would act
like long-term storage.  The programmer would be responsible for knowing
what code was resident on-chip and would write the program accordingly. 
As such, this would not "complicate the timing equations with events
that take hundreds of cycles", unless the program was utilizing a
virtual memory scheme.

You mention that "With old slow DRAM only 140mips max, well below the
500 in the CPU.  In faster SRAM it goes up to 250.  With a faster memory
interface good code could keep close to the 500."  If most, if not all
of the code of the program on-chip, wouldn't the memory interface run at
the full 500?  The only off-chip memory accesses would be for additional
data that could be loaded a full memory page at a time, taking advantage
of page-mode access.  Wouldn't this be the most efficient method of
utilizing memory space?

I know that you have made certain choices in your work based on what was
available to you.  I am asking my questions so that I may learn about
what is possible and what trade-offs will need to be made.  Whether I
will be able to implement the ideas may be a different story, but only
time will tell.  You have real-world experience with this topic, so you
are the most qualified person I know to ask.  Is cost the only
consideration for placing the CPU and memory on the same chip?  You
mentioned that they are usually made with different processes, but you
alluded to the option of designing a CPU to take advantage of memory
processes.  Would doing so affect the stability of the processor, or
limit the types of circuits that could be used in the processor design?

Again, I want to thank you for the time you have devoted to the
following you and Chuck have created.

			-Alan Tutt
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