Re: Chucks address WAS f21 docs
At 05:45 PM 6/11/2000 -0700, I wrote:
>At 09:03 PM 6/11/2000 -0700, M. Simon wrote:
>>At 06:13 AM 6/11/00 -0700, Cyan Cernwnos wrote:
>>> > Chuck introduced the bus with
>>> > half the bits positive and half the bits negative.
>>>
>>>I don't understand. Why would an efficient
>>>incrementing system invert every other bit?
>>
>>Fewer transistors.
>
>...in the carry-chain. He uses a ripple-carry adder, with a little
>carry look-ahead that balances speed against the gate count.
>His idea saves an inverter delay per bit, noticeable at 20 bits,
>especially since his clock cycle is less than 20 inverter delays!
>
>It takes a while to get used to, both as a programmer and as a
>logic-analyser user debugging the thing. But we've talked about
>adding inverters at the chip edge (in/out) that would make the
>whole issue moot.
^^^^^^^^^^^^^^^^
I got carried away here: we talked about it, but Chuck didn't agree
that it was worth it, AND it still requires some thought about the
difference between bit-patterns and numbers. I didn't pursue it enough
to figure out whether I could remove ALL the external issues.
(Just want to avoid a 'heated discussion' about it, although reasoned
research is always welcome, especially around these wonderfully weird
ideas Chuck has had.)
-John
